GM82C803CN Datasheet, PDF (21/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
BIT 5 DIR
This bit controls the parallel port direction. A logic 0 indicates that the parallel port is in output mode and a
logic 1 indicates that parallel port is in input mode. In the compatible mode, this bit is always 0 regardless of
the state of this bit.
BIT 6,7
These bits are reserved and always 0.
3.2 EPP MODE
The EPP mode is high speed and bi-direction protocol and the data rate is up to 2M byte/sec. The EPP mode
provides for greater throughput than compatible mode by supporting faster transfer time and a mechanism that
allows the host to address peripheral device registers directly. The PRIME3C supports EPP mode(IEEE
1284) that can be selected through the FSR. When PRIME3C is in EPP mode, the PRIME3C also supports
PS/2 style bi-direction mode. The PRIME3C supports 2 EPP modes: EPP ver. 1.7 and ver. 1.9. The EPP
version is selected by the bit 4 of PCR and the default version is ver. 1.9. There are 4 operations in EPP
mode: address write, address read, data write and data read. Before accessing the EPP registers, the software
must write 0’s to bit0,1,3 and 5 of CTR because the output pins and direction of data are controlled by EPP
hardware. If the bit 6 of PCR is 1, the software must control direction of data by setting and resetting the bit5
of CTR(direction bit). The EPP operations are closely related with the system timing(I/O read and write). For
this reason, a timer is required to prevent system from being locked up. If more than 10 usec have elapsed
from start of the EPP cycle, the timeout timer generates timeout error and sets the timeout bit of STR. This
timeout condition is available only in EPP ver. 1.9.
The EPP mode has 8 addressable ports. These ports are defined as follows.
data port
base address + 00H
status port
base address + 01H
control port
base address + 02H
EPP address port base address + 03H
EPP data port 0 base address + 04H
EPP data port 1 base address + 05H
EPP data port 2 base address + 06H
EPP data port 3 base address + 07H
DATA REGISTER (base address + 00H)
This register is Compatible parallel port and same with DTR register in Compatible mode.
STATUS REGISTER (base address + 01H)
This register is same with STR register in Compatible mode.
CONTROL REGISTER (base address + 02H)
This register is same with CTR register in Compatible mode.
EPP ADDRESS REGISTER (base address + 03H)
This register is cleared at initialization by RESET. A write operation to this port initiates an EPP ADDRESS
WRITE operation that is used for EPP device/register selection. A read operation to this port generates EPP
ADDRESS READ operation.
EPP DATA PORT 0 REGISTER (base address + 04H)
This register is cleared at initialization by RESET. Access to this port initiate EPP DATA WRITE or EPP
DATA READ operations with bit[7:0].