GM82C803CN Datasheet, PDF(31/84 Page) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

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GM82C803CN Datasheet, PDF (31/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

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GM82C803CN

FIFO Threshold

Example

1 byte

2 byte

8 byte

15 byte

Maximum Delay to Servicing

at 500 Kbps Data Rate

1 16

2 16

8 16

15 16

1.5 = 14.5

1.5 = 30.5

1.5 = 126.5

1.5 = 238.5

At the start of a command, the FIFO action is always disabled and command parameters must be sent

based upon the RQM and DIO bit settings. As the FDC enters the command execution phase, it clears

the FIFO of any data to ensure that invalid data is not transferred. An overrun or underrun will terminate

the current command and the transfer of data. Disk Write will complete the current sector by generating

a 00H pattern and valid CRC.

Main Status Register (MSR)

MSR indicates the current status of the disk controller. It is always available to be read and controls the

flow of data to and from the Data Register (FIFO).

Table 4-10 Main Status Register

Bit

Symbol

Name

RQM

Request for

Master

DIO

Data In/Out

Function

Indicates that host can access the Data Register if one.

No access should be attempt if zero.

Indicates the direction of the data transfer only when

RQM is one. If one, transfer is from Data Register to

host. If zero, transfer is from host to Data Register.

EXM

Execution

Mode

This bit is set to one only during execution phase in

Non-DMA mode. When zero, execution phase has e-

nded and result phase has started. EXM remains 0 if

DMA mode is selected.

Controller

Busy

F3B

FDD 3 Busy

A Read or Write is in progress. FDC will not accept

any other command.

If one, FDD number 3 is in seek mode. It will not ac-

cept Read or Write Command. Cleared after reading

the first byte in the Result Phase of the Sense Interru-

pt Command for this drive..

F2B

FDD2 Busy

Same as above for FDD2.

F1B

FDD1 Busy

Same as above for FDD1.

F0B

FDD0 Busy

Same as above for FDD0.

Result Phase Status Register (ST0, ST1, ST2, ST3)

The result phase of a command contains bytes that hold status information. The four result phase status regis-

ters are read from the Data Register only during the result phase of certain commands. Those may be read only

after successfully completing a command. The particular command which has been executed determines how

many of the Status Registers will be read.

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