DS80C390_00 Datasheet, PDF (83/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

RXS
Bit 4
DS80C390 High-Speed Microcontroller User’s Guide Supplement
CAN 1 Receive Status. This bit indicates whether or not messages have been
received since the last read of the CAN 1 Status Register. RXS is only set by the
CAN 1 logic and must be cleared by the Microcontroller software, the CRST bit,
or a system Reset.
1 = The meaning of RXS=1 is dependent on the Autobaud bit, AUTOB.
AUTOB=0, RXS = 1 indicates that a message has been both successfully
received and stored in one of the message centers by CAN 1 since the last
read of the CAN 1 Status Register.
AUTOB=1, RXS = 1 indicates that a message has been successfully received
by CAN 1 since the last read of the CAN 1 Status Register. Note that
messages that are successfully received without errors but do not pass the
arbitration filtering will still set the RXS bit.
0 = No messages have been successfully received since the last read of the CAN 1
Status Register.
When STIE= 1 and the RXS bit transitions from 0 to 1, the CAN Interrupt
Register (C1IE;A5h) will change to 01h to indicate a pending interrupt due to a
change in the CAN Status Register. Reading any bit in the C1S register will clear
the pending interrupt, causing the C1IE register to change to 00h if no interrupts
are pending or the appropriate value if a lower priority message center interrupt is
pending. If a second successful reception is detected prior to or after the clearing
of the RXS bit in the Status Register, a second status change interrupt flag will be
set, issuing a second interrupt. Each new successful reception will generate an
interrupt request independent of the previous state of the RXS bit, as long as the
CAN Status Register has been read to clear the previous status change interrupt
flag. Note that if software changes RXS from 0 to 1, an artificial Status Change
Interrupt (STIE=1) will be generated. Thus, if RXS was previously set to 0 and a
reception was successful, RXS will be set to 1 and an enabled interrupt may be
asserted. An interrupt may be asserted (if enabled) if software changes RXS from
0 to 1. If RXS was previously set to 1 and a reception was successful, RXS
remains set and an interrupt may be asserted if enabled. No interrupt will be
asserted if software attempts to set RXS=1 while the bit is already set.
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