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DS80C390_00 Datasheet, PDF (56/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement
DS80C390 High-Speed Microcontroller User’s Guide Supplement
Serial Port Control (SCON1)
7
6
5
4
3
2
1
0
SFR C0h SM0/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1
RI_1
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
SM0-2
Bits 7-5
Serial Port 1 Mode. These bits control the mode of serial port 1 as shown
below. In addition, the SM0 and SM2 bits have secondary functions as shown
below.
SM0
0
0
0
SM1
0
0
1
SM2
0
1
X
MODE
0
0
1
FUNCTION
Synchronous
Synchronous
Asynchronous
LENGTH
8 bits
8 bits
10 bits
1
0
0
1
0
1
1
1
0
1
1
1
2
Asynchronous
11 bits
1
Asynchronous w/
11 bits
Multiprocessor communication
3
Asynchronous
11 bits
3
Asynchronous w/
11 bits
Multiprocessor communication
PERIOD
12 tCLK
4 tCLK
Timer 1 or 2
baud rate equation
64 tCLK (SMOD=0)
32 tCLK (SMOD=1)
64 tCLK (SMOD=0)
32 tCLK (SMOD=1)
Timer 1 or 2
baud rate equation
Timer 1 or 2
baud rate equation
SM0/FE_1
Bit 7
SM1_1
Bit 6
SM2-2
Bit 5
REN_1
Bit 4
Framing Error Flag. When SMOD0 (PCON.6)=0, this bit (SM0) is used to
select the mode for serial port 1. When SMOD0 (PCON.6)=1, this bit (FE) will
be set upon detection of an invalid stop bit. When used as FE, this bit must be
cleared in software. Once the SMOD0 bit is set, modifications to this bit will not
affect the serial port mode settings. Although accessed from the same register,
internally the data for bits SM0 and FE are stored in different locations.
No alternate function.
Multiple CPU Communications. The function of this bit is dependent on the
serial port 0 mode.
Mode 0: Selects 12 tCLK or 4 tCLK period for synchronous serial port 0 data
transfers.
Mode 1: When set, reception is ignored (RI_1 is not set) if invalid stop bit
received.
Mode 2/3: When this bit is set, multiprocessor communications are enabled in
modes 2 and 3. This will prevent the RI_1 bit from being set, and an
interrupt being asserted, if the 9th bit received is not 1.
Receive Enable. This bit enables/disables the serial port 1 receiver shift register.
0 = Serial port 1 reception disabled.
1 = Serial port 1 receiver enabled (modes 1, 2, 3). Initiate synchronous reception
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