DS80C390_00 Datasheet, PDF (28/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

TB8_0
Bit 3
RB8_0
Bit 2
TI_0
Bit 1
RI_0
Bit 0
DS80C390 High-Speed Microcontroller User’s Guide Supplement
9^th Transmission Bit State. This bit defines the state of the 9^th transmission bit
in serial port 0 modes 2 and 3.
9^th Received Bit State. This bit identifies that state of the 9^th reception bit of
received data in serial port 0 modes 2 and 3. In serial port mode 1, when
SM2_0=0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0.
Transmitter Interrupt Flag. This bit indicates that data in the serial port 0
buffer has been completely shifted out. In serial port mode 0, TI_0 is set at the
end of the 8^th data bit. In all other modes, this bit is set at the end of the last data
bit. This bit must be manually cleared by software.
Receiver Interrupt Flag. This bit indicates that a byte of data has been received
in the serial port 0 buffer. In serial port mode 0, RI_0 is set at the end of the 8^th
bit. In serial port mode 1, RI_0 is set after the last sample of the incoming stop bit
subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample
of RB8_0. This bit must be manually cleared by software.
Serial Data Buffer 0 (SBUF0)
7
6
5
SFR 99h SBUF0.7 SBUF0.6 SBUF0.5
RW-0 RW-0 RW-0
4
SBUF0.4
RW-0
3
SBUF0.3
RW-0
2
SBUF0.2
RW-0
1
SBUF0.1
RW-0
0
SBUF0.0
RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
SBUF0.7-0
Bits 7-0
Serial Data Buffer 0. Data for serial port 0 is read from or written to this
location. The serial transmit and receive buffers are separate registers, but both
are addressed at this location.
Extended Stack Pointer Register (ESP)
7
6
5
4
3
2
1
0
SFR 9Bh
1
1
1
1
1
1
ESP1
ESP0
R-1
R-1
R-1
R-1
R-1
R-1
RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
Bits 7-2
ESP.1-0
Bits 1-0
Reserved
Extended Stack Pointer. This register contains the upper 2 bits of the 10-bit
stack pointer. When the SA bit is set, any overflow of the SP from FFh to 00h
will increment the ESP by 1, and any underflow of the SP from 00h to FFh will
decrement the ESP by 1. The ESP register is ignored when SA = 0, but is still
read/write accessible. Configuring the 4K block of SRAM as program and/or data
memory (IDM1,IDM0=11b) will disable the extended stack mode. Internal logic
will take into consideration the programming conditions imposed by the SA,
IDM1 and IDM0 bits within the MCON register, to allow access to the 1K Stack
Memory. See ACON register for more detail.
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