DS80C390_00 Datasheet, PDF (47/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

ETI
Bit 6
ERI
Bit 5
INTRQ
Bit 4
EXTRQ
Bit 3
MTRQ
Bit 2
DS80C390 High-Speed Microcontroller User’s Guide Supplement
CAN 0 Message Center 1 Enable Transmit Interrupt. Setting ETI to a 1
will enable a successful CAN 0 transmission in message center 1 to set the
INTRQ bit for this message center which in turn will issue an interrupt to the
microcontroller. When ETI is cleared to 0 a successful transmission will not
set INTRQ bit and will not generate an interrupt. Note that the ETI bit located
in Message Center 15 is ignored by the CAN module, since the message
center 15 is a receive only message center.
CAN 0 Message Center 1 Enable Receive Interrupt. Setting ERI to a 1
will enable a successful CAN 0 reception and storage in message center 1 to
set the INTRQ bit for this message center which in turn will issue an interrupt
to the microcontroller. When ERI is cleared to 0 a successful reception will
not set the INTRQ bit and as such will not generate an interrupt.
CAN 0 Message Center 1 Interrupt Request. This bit serves as a CAN
interrupt flag, indicating the successful transmission or reception of a
message in this message center. INTRQ is automatically set when ERI=1 and
message center 1 successfully receives and stores a message. The INTRQ bit
is also set to a 1 when ETI is set and the CAN 1 logic completes a successful
transmission. The INTRQ interrupt request must be also enabled via the EA
global mask in the IE SFR register if the interrupt is to be acknowledged by
the microcontroller interrupt logic. This flag must be cleared via software.
CAN 0 Message Center 1 External Transmit Request. When EXTRQ is
cleared to a 0, there are no pending requests by external CAN nodes for this
message. When EXTRQ is set to a 1, a request has been made for this
message by an external CAN node, but the CAN 0 controller has not yet
completed the service request. Following the completion of a requested
transmission by a message center programmed for transmission (T/ R = 1),
the EXTRQ bit will be cleared by the CAN 0 controller. A remote request is
only answered by a message center programmed for transmission (T/ R = 1)
when DTUP = 1 and TIH = 0, i.e. when new data was loaded and is not being
currently modified by the micro. Note that a message center programmed for
a receive mode (T/ R = 0) will also detect a remote frame request and will set
the EXTRQ bit in a similar manner, but will not automatically transmit a data
frame and as such will not automatically clear the EXTRQ bit.
CAN 0 Message Center 1 Microcontroller Transmit Request. When set,
this bit indicates that the message center is requesting that a message be
transmitted. The bit is cleared when the transmission is complete, allowing
this bit to be used to both initiate and monitor the progress of the
transmission. The bit can be set via software or the CAN module, depending
on the state of the Transmit/Receive bit in the CAN 0 Message 1 Format
Register (located in MOVX space). This bit is cleared when the CRST bit is
set, the CAN module experiences a system reset, or the conditions described
below. Note that the MTRQ bit located in Message Center 15 is ignored by
the CAN module, since the Message Center 15 is a receive only message
center.
T/ R =0 (receive)
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