DS80C390_00 Datasheet, PDF (72/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
Multiplier B Register (B)
7
6
SFR D4h
RW-0 RW-0
5
RW-0
4
RW-0
3
RW-0
2
RW-0
1
RW-0
0
RW-0
R=Unrestricted Read, W=Unrestricted Read, -n=Value after Reset
Bits 7-0
Multiplier B Register. The MB Register is used as both a source and result
register for various arithmetic accelerator functions. When in the source mode it
is loaded with the dividend for divide operations and the multiplier when
performing multiply operations. The MA register also holds the remainder of the
divide operations.
The MB register can receive or hold up to a 32-bit result, accessed via a series of
sequential writes to or reads from the register. Details of the sequencing are
explained in the arithmetic accelerator section of the User’s Guide.
Multiplier C Register (C)
7
6
SFR D5h
RW-0 RW-0
5
RW-0
4
RW-0
3
RW-0
2
RW-0
1
RW-0
0
RW-0
R=Unrestricted Read, W=Unrestricted Read, -n=Value after Reset
Bits 7-0
Multiplier C Register. The MC Register allows access to the 40-bit accumulator
register for the arithmetic accelerator. Each time a multiply or divide (but not
shift or normalization) function is performed with the arithmetic accelerator the
result is added to the previous value in the MC register.
Data is read from the 40-bit accumulator MSB first, and five read operations must
be performed to read the entire value. Writes to the accumulator are performed
LSB first, but software may write as few registers as needed (i.e., 2 in the case of
a 16-bit value) provided the unloaded registers have been previously initialized to
00h. Details of the sequencing are explained in the arithmetic accelerator section
of the User’s Guide.
All 40 bits of the accumulator are cleared by a system reset, the setting of the
CLM bit or the setting of the MST bit in the MCNT1 SFR. The register can also
be cleared by performing five writes of 00h to the MC register.
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