DS80C390_00 Datasheet, PDF (14/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

Power Control (PCON)
7
6
SFR 87h SMOD_0 SMOD0
RW-0 RW-0
DS80C390 High-Speed Microcontroller User’s Guide Supplement
5
OFDF
RW-0*
4
ODFE
RW-0*
3
FG1
RW-0
2
FG0
RW-0
1
STOP
RW-0
0
IDLE
RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset, *=See description
SMOD_0
Bit 7
SMOD0
Bit 6
OFDF
Bit 5
OFDE
Bit 4
GF1
Bit 3
GF0
Bit 2
STOP
Bit 1
IDLE
Bit 0
Serial Port 0 Baud Rate Doubler Enable. This bit enables/disables the
serial baud rate doubling function for Serial Port 0.
0 = Serial Port 0 baud rate will be that defined by baud rate generation
equation.
1 = Serial Port 0 baud rate will be double that defined by baud rate generation
equation.
Framing Error Detection Enable. This bit selects function of the
SCON0.7 and SCON1.7 bits.
0 = SCON0.7 and SCON1.7 control the SM0 function defined for the
SCON0 and SCON1 registers.
1 = SCON0.7 and SCON1.7 are converted to the Framing Error (FE) flag for the
respective Serial Port.
Oscillator Fail Detect Flag. When set, this bit indicates that the preceding reset
was caused by the detection of the crystal oscillator frequency falling below
approximately 30 kHz while the OFDE bit was set. This bit must be cleared by
software. This bit not altered (and no reset will be generated) under the following
conditions:
1. OFDE=0
2. An oscillator halt associated with entering STOP mode.
3. An oscillator halt associated with running from the internal ring oscillator.
Oscillator Fail Detect Enable. When the OFDE=1, a system reset will be
generated any time the crystal oscillator frequency falls below approximately 30
kHz. When the OFDE bit is cleared to a logic 0, no reset will be issued when the
crystal falls below 30 kHz. The OFDE is cleared to a logic 0 by any reset source.
General Purpose User Flag 1. This is a bit-addressable, general-purpose flag
for software control.
General Purpose User Flag 0. This is a bit-addressable, general-purpose flag
for software control.
Stop Mode Select. Setting this bit will stop program execution, halt the CPU
oscillator, and internal timers, and place the CPU in a low-power mode. This bit
will always be read as a 0. Setting this bit while the IDLE=1 will place the
device in an undefined state.
Idle Mode Select. Setting this bit will stop program execution but leave the CPU
oscillator, timers, serial ports, and interrupts active. This bit will always be read
as a 0.
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