DS80C390_00 Datasheet, PDF (148/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
Node detects the 14th consecutive dominant bit (in
case of an active error flag or an overload flag), or
detects the 8th consecutive dominant bit following a
passive error flag, or after a sequence of additional
eight consecutive dominant bits.
Transmit Error Counter incremented by 8.
Receive Error Counter incremented by 8.
Message is successfully transmitted (acknowledge
Transmit Error Count is decremented by 1
received and no error until end of frame is complete) (unless it was already 0).
A message has been successfully received (reception
without error up to the acknowledge slot and the
successful sending of the acknowledge bit), and the
receive error count was between 1 and 127.
Receive Error Counter decremented by 1.
A message has been successfully received (reception
without error up to the acknowledge slot and the
successful sending of the acknowledge bit), and the
receive error count was greater than 127.
Receive Error Counter is set to a value
between 119 and 127.
A node is error passive when the transmit error count equals or exceeds 128, or when the receive error
count equals or exceeds 128. An error condition letting a node become error passive causes the node to
send an active error flag. An error passive node becomes error active again when both the transmit error
count and the receive error count are less than or equal to 127.
A node is bus off when the transmit error count is greater than or equal to 256. A bus off node will
become error active (no longer bus off) with its error counters both set to 0 after 128 occurrence of 11
consecutive recessive bits have been monitored on the bus.
After exceeding the error passive limit (128), the receive error counter will not be increased any further.
When a message was received correctly, the counter is set again to a value between 119 and 127
(compare with CAN 2.0B specification). After reaching the “bus off“ status, the transmit error counter is
undefined while the receive error counter is cleared and changes its function. The receive error counter
will be incremented after every 11 consecutive recessive bits on the bus. These 11 bits correspond to the
gap between two messages on the bus. If the receive error counter reaches the count 128, following the
bus off recovery sequence, the CAN module changes automatically back to the status of “bus on” and
then sets SWINT = 1. After setting SWINT, all internal flags of the CAN module are reset and the error
counters are cleared. A recovery from a bus off condition does not alter any of the previously
programmed MOVX memory values and will also not alter SFR registers, apart from the transmit and
receive error SFR registers and the error conditions displayed in CAN Status Register. The bus timing
will remain as previously programmed.
Bit Timing
Bit timing in the CAN 2.0B specification is based on a unit called the nominal bit time. The nominal bit
time is further subdivided into four specific time periods.
1. The SYNC_SEG time segment is where an edge is expected when synchronizing to the CAN Bus.
2. The PROP_SEG time segment is provided to compensate for the physical times associated with
the CAN Bus network
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