DS80C390_00 Datasheet, PDF (104/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
ADDENDUM TO SECTION 10: PARALLEL I/O
Changes to this section primarily involve the additional functionality associated with Port 4 and 5, and the
use of Port 1 as the address LSB in non-multiplexed memory mode. Because the DS80C390 is a
ROMless device, Port 0 and 2 do not support general purpose I/O.
Port 1
General Purpose I/O
When the device is operating in multiplexed memory mode ( MUX pin is tied to a logic low) port 1
serves as a general purpose I/O port. Data written to the port latch serves to set both level and direction of
the data on the pin. More detail on the functions of port 1 pins configured for general purpose I/O is
provided under the description of port 1 and port 3 in the High-Speed Microcontroller User's Guide.
Non-multiplexed Address Bus A0-A7
When the device is operating in non-multiplexed memory mode ( MUX pin is tied to a logic high) port 1
serves LSB of the external address bus. When operating as the LSB of the address bus the port 1 pins
have extremely strong drivers that allow the bus to move 100 pF loads with the timing shown in the
electrical specifications.
When used as an address bus, the A0-7 pins will provide true drive capability for both logic levels. No
pull-ups are needed. In fact, pull-ups will degrade the memory interface timing. Members of the High-
Speed Microcontroller family employ a two-state drive system on A0-7. That is, the pin is driven hard for
a period to allow the greatest possible setup or access time. Then the pin states are held in a weak latch
until forced to the next state or overwritten by an external device. This assures a smooth transition
between logic states and also allows a longer hold time. In general, the data is held (hold time) on A0-7
until another device overwrites the bus. This latch effect is generally transparent to the user.
Current-limited transitions
The DS80C390 does not employ the current-limited transition feature described in the High-Speed
Microcontroller User's Guide.
Ports 4 and 5
Ports 4 and 5 are general purpose I/O ports with optional special functions associated with each pin.
Enabling the special function automatically converts the I/O pin to that function. To insure proper
operation, each alternate function pin should be programmed to a logic 1.
The drive characteristics of these pins may change depending on whether the pin is configured for general
I/O or as the special function associated with that pin. When in I/O mode, the logic 0 is created by a
strong pull-down. The logic 1 is created by a strong transition pull-up that changes to a weak pull-up.
When a pin is configured in its alternate function, and that function concerns memory interfacing (A16-
A17, PCE0 − 3, or CE0 − 3 ) the pins will be driven using the stronger memory interface values shown in
the DC electrical characteristics of the data sheet.
OUTPUT FUNCTIONS
Although 8051 I/O ports appear to be true I/O, their output characteristics are dependent on the individual
port and pin conditions. When software writes a logic 0 to the port for output, the port is pulled to ground.
When software writes a logic 1 to the port for output, ports 1, 3, 4, or 5 will drive weak pull-ups (after the
strong transition from 0 to 1). Port 0 will go tri-state. Thus as long as the port is not heavily loaded, true
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