DS80C390_00 Datasheet, PDF (102/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
P5CNT.2-0
000(default)
100
101
110
111
Port 5 Pin Function
(MOVX Memory Chip Enables)
P5.7 P5.6 P5.5 P5.4
I/O I/O I/O I/O
I/O
I/O
I/O _PCE0
I/O
I/O
PCE1 PCE0
I/O
PCE2 PCE1 PCE0
PCE3 PCE2 PCE1 PCE0
The following table illustrates how memory is segmented based on the setting of the Port 4 P4.7-4
Configuration Control bits (P4CNT.5-3)
PROGRAM MEMORY CHIP ENABLE BOUNDARIES Table 6-3
P4CNT.5-3
CE0
CE1
CE2
CE3
000
100
101
110
111(default)
0h-7FFFh
0h-1FFFFh
0h-3FFFFh
0h-7FFFFh
0-FFFFFh
8000h-FFFFh
20000h-3FFFFh
40000h-7FFFFh
80000h-FFFFFh
100000h-1FFFFFh
10000h-17FFFh
40000h-5FFFFh
80000h-BFFFFh
100000h-17FFFFh
200000h-2FFFFFh
18000h-1FFFFh
60000h-7FFFFh
C0000h-FFFFFh
180000h-1FFFFFh
300000h-3FFFFFh
Maximum Memory
size per Chip Enable
32 kilobytes
128 kilobytes
256 kilobytes
512 kilobytes
1 megabyte
Following any reset, the device defaults to 16-bit mode addressing. In 16-bit addressing mode the device
will be configured with P4.7-P4.4 as address lines and P4.3-P4.0 configured as CE3 - 0 , with the first
program fetch being performed from 00000h with CE0 active (low).
Using the combined chip enable signals
The DS80C390 incorporates a feature allowing PCEx and CEx signals to be combined. This is useful
when incorporating modifiable code memory as part of a bootstrap loader or for in-system
reprogrammability. Setting the one or more PDCE3 − 0 bits (MCON.3-0) causes the corresponding chip
enable signal to be asserted for both MOVC and MOVX operations. Write access to combined program
and data memory blocks is controlled by the WR signal, and read access is controlled by the PSEN
signal. This feature is especially useful if the design achieves in-system reprogrammability via external
Flash memory, in which a single device is accessed via both MOVC instructions (program fetch) and
MOVX write operations (updates to code memory). In this case, the internal SRAM is placed in the
program/data configuration and loaded with a small bootstrap loader program transferred from the
external Flash memory. The device then executes the internal bootstrap loader routine to modify/update
the program memory located in the external Flash memory.
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