DS80C390_00 Datasheet, PDF (18/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

Clock Control (CKCON)
7
6
SFR 8Eh WD1 WD0
RW-0 RW-0
DS80C390 High-Speed Microcontroller User’s Guide Supplement
5
T2M
RW-0
4
T1M
RW-0
3
T0M
RW-0
2
MD2
RW-0
1
MD1
RW-0
0
MD0
RW-1
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
WD1, WD0
Bits 7-6
Watchdog Timer Mode Select 1-0. These bits select the watchdog timer time-
out period, which determines the timing of the watchdog timer interrupt and the
watchdog timer reset.
WD1
0
0
1
1
WD0
0
1
0
1
Interrupt time-out
2¹⁷ system clocks
2²⁰ system clocks
2²³ system clocks
2²⁶ system clocks
Reset time-out
2¹⁷ + 512 system clocks
2²⁰ + 512 system clocks
2²³ + 512 system clocks
2²⁶ + 512 system clocks
The system clock relates to the external clock as follows:
Clock Mode
Frequency Multiplier (4x)
Frequency Multiplier (2x)
Divide by 4
Power Management Mode
External clocks per system clock
0.25
0.5
1
256
T2M
Bit 5
T1M
Bit 4
T0M
Bit 3
Timer 2 Clock Select. This bit controls the division of the system clock that
drives Timer 2. This bit has no effect when the timer is in baud rate generator or
clock output modes. Clearing this bit to 0 maintains 80C32 compatibility. This bit
has no effect on instruction cycle timing.
0 = Timer 2 uses a divide by 12 of the crystal frequency.
1 = Timer 2 uses a divide by 4 of the crystal frequency.
Timer 1 Clock Select. This bit controls the division of the system clock that
drives Timer 1. Clearing this bit to 0 maintains 80C32 compatibility. This bit
has no effect on instruction cycle timing.
0 = Timer 1 uses a divide by 12 of the crystal frequency.
1 = Timer 1 uses a divide by 4 of the crystal frequency.
Timer 0 Clock Select. This bit controls the division of the system clock that
drives Timer 0. Clearing this bit to 0 maintains 80C32 compatibility. This bit
has no effect on instruction cycle timing.
0 = Timer 0 uses a divide by 12 of the crystal frequency.
1 = Timer 0 uses a divide by 4 of the crystal frequency.
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