DS80C390_00 Datasheet, PDF (48/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

ROW/TIH
Bit 1
DS80C390 High-Speed Microcontroller User’s Guide Supplement
When software sets this bit, a remote frame request previously loaded into the
message center will be transmitted. The CAN 0 Module will clear this bit
following the successful transmission of the frame request message.
T/ R =1 (transmit)
When software sets this bit, a data frame previously loaded into the message
center will be transmitted. When T/ R = 1, the MTRQ bit will also be set by the
CAN 0 controller at the same time that the EXTRQ bit is set by a message request
from an external node.
CAN 0 Message Center 1 Receive Overwrite/Transmit Inhibit. The
Receive Overwrite (ROW) and Transmit Inhibit (TIH) bits share the same bit
location. When T/ R = 0 the bit has the ROW function, serving as a flag that
an overwrite of incoming data may have occurred. When T/ R = 1 the bit has
the Transmit Inhibit function, allowing software to disable the transmission
of a message while the data contents are being updated.
Receive Overwrite: (T/R = 0, ROW is Read Only)
The CAN 0 controller automatically sets this bit 0 if a new message is received
and stored while the DTUP bit was still set. When set, ROW indicates that the
previous message was potentially lost and may not have been read, since the
microcontroller had not cleared the DTUP bit prior to the new load. When ROW
= 0, no new message has been received and stored while DTUP was set to ‘1’
since this bit was last cleared. Note that the ROW bit will not be set when the
WTOE bit is cleared to a 0, since all overwrites are disabled. This is due to the
fact that even if the incoming message matches the respective message center that
as long as DTUP = 1 in the respective message center, the combination of WTOE
= 0 and DTUP = 1 will force the CAN module to ignore the respective message
center when the CAN is processing the incoming data.
ROW is cleared by the CAN module when software clears the DTUP bit
associated with that message center. INTRQ is automatically set when the
ERI=1 and message center 1 successfully receives and stores a message.
ROW will reflect the actual message center relationships for message centers
1 to 14. Message center 15 utilizes a special shadow message buffer, and the
ROW bit for that message center indicates an overwrite of the buffer as
opposed to the actual message center 15. The ROW bit for message center 15
is cleared once the shadow buffer is loaded into the message center 15, and
the shadow buffer is cleared to allow a new message to be loaded. The
shadow buffer is automatically loaded into message center 15 when the
microcontroller clears the DTUP and EXTRQ bits in message center 15.
Transmit Inhibit: (T/R = 1, TIH is unrestricted Read/Write)
The TIH allows the microcontroller to disable the transmission of the
message when the data contents of the message are being updated. TIH = 1
directs the CAN 0 controller not to transmit the associated message. TIH = 0
enables the CAN 0 controller to transmit the message. If TIH = 1 when a
remote frame request is received by the message center, EXTRQ will be set
to a 1. Following the Remote Frame Request and after the microcontroller
has established the proper data to be sent, the microcontroller will clear the
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