DS80C390_00 Datasheet, PDF (37/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

CRST
Bit 3
AUTOB
Bit 2
ERCS
Bit 1
DS80C390 High-Speed Microcontroller User’s Guide Supplement
CAN 0 Reset. Setting this bit via a Timed Access write will reset all CAN 0
registers in the SFR map to their reset default states. The module will reset the
registers immediately upon setting this bit, or following the completion of the
current reception, transmission, arbitration failure, or error condition on CAN 0.
Software can poll the CRST bit to ascertain whether the microcontroller has
successfully reset the registers (CRST =1) or is waiting for a current CAN
operation to complete (CRST =0) before resetting the registers. Setting the CRST
bit also clears the transmit and receive error counters and sets the SWINT bit.
CRST must be cleared by software to remove the CAN reset. The state of the
SWINT and BUSOFF bits determines the action of the device when the CRST bit
is cleared.
CAN 0 Autobaud. Setting this bit allows the CAN 0 module to establish proper
CAN bus timing without disrupting the normal data flow between other nodes on
the CAN Bus. When in the autobaud mode, incoming data on the C0RX pin is
internally ANDed with transmit data generated by the CAN 0 module. An internal
loop back feeds this combined data stream back into the input of the CAN 0
module. At the same time, C0TX pin is placed into a recessive state to prevent
driving non-synchronized data (creating CAN Bus errors to other nodes) while
attempting to synchronize the processor with the CAN Bus.
With AUTOB = 1, the microcontroller auto-baud algorithm will make use of the
CAN 0 Status Register RXS and error status bits to determine when a message is
successfully received (when AUTOB =1, a successful receive does not require a
store). Each successive baud rate attempt is proceeded by the microcontroller
clearing the transmit and receive error counters via a write of 00h to the Transmit
Error SFR Register and a read of the CAN 0 Status Register to clear the previous
Status Change Interrupt. Note that a write to the Transmit Error SFR Register
automatically resets the CAN fault confinement state machine to an initial (error
active) state if the error counters are cleared to 00h. If, however, the error counters
are programmed to a value greater than 128, the CAN module will be in a error
passive state. Appropriate flags are set when the error counter is written with any
value. A write of the Status Register is also used to remove the previous error
value in the ER2-0 bits. Clearing the error counters will also clear the CECE bit, if
set.
When BUSOFF = 1, software is prohibited from writing to the error counters by
virtue of the fact that the SWINT bit is also forced to a 0 state during the period
that the CAN module performs a bus recovery and power up sequence. Once the
CAN module has removed itself from the Bus Off condition it will also clear
BUSOFF = 0, set SWINT = 1, and will clear both the transmit and receive error
counters to 00h.
CAN 0 Error Count Select. This bit selects the number of transmit or receive
errors that will cause the CAN 0 Error Count Exceeded bit, CECE (C0S.6), to be
set.
0 = CECE bit set when the transmit or receive error counters exceed 95 errors.
1 = CECE bit set when the transmit or receive error counters exceed 127 errors.
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