DS80C390_00 Datasheet, PDF (61/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
Memory Control Register (MCON)
7
6
5
4
3
2
1
0
SFR C6h IDM1 IDM0 CMA
1
PDCE3 PDCE2 PDCE1 PDCE0
RT-0
RT-0
RT-0
R-1
RT-0
RT-0
RT-0
RT-0
R=Unrestricted Read, T=Timed Access Write Only, -n=Value after Reset
IDM1, IDM0
Bits 7-6
CMA
Bit 5
Bit 4
PDCE3
Bit 3
PDCE2
Bit 2
Internal Data Memory Configuration Bits 1-0. These bits establish both the
address and type (data and/or program) of the internal 4 KB internal SRAM as
shown in the table below.
Note that a special lockout feature prevents the use of the Program and/or Data
Memory configuration (IDM1, IDM0 = 11b) and the 10-bit stack pointer (SA=1)
at the same time. The IDM1, IDM0 bits can be set to 11b only when the SA bit
(ACON.2) is cleared, and the SA bit cannot be set while the IDM1, IDM0 bits are
equal to 11b. Attempts to modify the IDMx or SA bits in these situations will fail
and the bit(s) will remain unchanged.
4 KB Internal SRAM
IDM1 IDM0 Memory Location Memory Assignment
0
0
00F000h-00FFFFh Data Memory
0
1
000000h-000FFFh Data Memory
1
0
400000h-400FFFh Data Memory
1
1
400000h-400FFFh Program and/or Data Memory
CAN Data Memory Assignment. This bit selects the address of the 256 byte
blocks of CAN Data Memory associated with both CAN controllers.
CMA
CAN 0 Memory Address CAN 1 Memory Address
0 (default)
00EE00h-00EEFFh
00EF00h-00EFFFh
1
401000h-4010FFh
401100h-4011FFh
Reserved
Program/Data Chip Enable 3. This bit selects whether the CE3 signal
functions as the chip enable for external program memory only (PDCE=0), or as
a merged chip enable for program and data memory (PDCE=1). When PDCE=1,
the microprocessor will use the PSEN signal instead of the RD signal when
reading from external MOVX memory. The Port 4 Control register (P4CNT)
determines the memory range associated with CE3. This bit is ignored if CE3
has not been previously enabled via the Port 4 Control register.
Program/Data Chip Enable 2. This bit selects whether the CE2 signal
functions as the chip enable for external program memory only (PDCE=0), or as
a merged chip enable for program and data memory (PDCE=1). When PDCE=1,
the microprocessor will use the PSEN signal instead of the RD signal when
reading from external MOVX memory. The Port 4 Control register (P4CNT)
determines the memory range associated with CE2 . This bit is ignored if CE2
has not been previously enabled via the Port 4 Control register.
61 of 155