DS80C390_00 Datasheet, PDF (54/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
Slave Address Mask Enable Register 0 (SADEN0)
7
6
5
4
3
2
1
0
SFR B9h ^{SADEN0.7 SADEN0.6 SADEN0.5 SADEN0.4 SADEN0.3 SADEN0.2 SADEN0.1 SADEN0.0}
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
SADEN0.7-0
Bits 7-0
Slave Address Mask Enable Register 0. This register functions as a mask when
comparing serial port 0 addresses for automatic address recognition. When a bit
in this register is set, the corresponding bit location in the SADDR0 register will
be exactly compared with the incoming serial port 0 data to determine if a
receiver interrupt should be generated. When a bit in this register is cleared, the
corresponding bit in the SADDR0 register becomes a don‘t care and is not
compared against the incoming data. All incoming data will generate a receiver
interrupt when this register is cleared.
Slave Address Mask Enable Register 1 (SADEN1)
7
6
5
4
3
SFR BAh ^{SADEN1.7 SADEN1.6 SADEN1.5 SADEN1.4 SADEN1.3}
RW-0 RW-0 RW-0 RW-0 RW-0
2
SADEN1.2
RW-0
1
SADEN1.1
RW-0
0
SADEN1.0
RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
SADEN1.7-0
Bits 7-0
Slave Address Mask Enable Register 1. This register functions as a mask when
comparing serial port 1 addresses for automatic address recognition. When a bit
in this register is set, the corresponding bit location in the SADDR1 register will
be exactly compared with the incoming serial port 1 data to determine if a
receiver interrupt should be generated. When a bit in this register is cleared, the
corresponding bit in the SADDR1 register becomes a don’t care and is not
compared against the incoming data. All incoming data will generate a receiver
interrupt when this register is cleared.
CAN 0 Message Center 11 Control Register (C0M11C)
7
6
5
4
3
2
SFR BBh MSRDY ETI
ERI INTRQ EXTRQ MTRQ
RW-0 RW-0 RW-0 RW-0 RC-0
R*-0
1
ROW/TIH
R*-0
0
DTUP
R*-0
R=Unrestricted Read, C=Clear Only, *= See description below, -n=Value after Reset
C0M11C
Bits 7-0
Operation of the bits in this register are identical to those found in the CAN 0
Message One Control Register (C0M1C;ABh). Please consult the description
of that register for more information.
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