DS80C390_00 Datasheet, PDF (27/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
Serial Port 0 Control (SCON0)
7
6
5
4
3
2
1
0
SFR 98h SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 T1_0
R1_0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
SM0-2
Bits 7-5
Serial Port Mode These bits control the mode of serial port 0. In addition the
SM0 and SM2_0 bits have secondary functions as shown below.
SM0
0
0
0
SM1
0
0
1
SM2
0
1
X
MODE
0
0
1
FUNCTION
Synchronous
Synchronous
Asynchronous
LENGTH
8 bits
8 bits
10 bits
1
0
0
1
0
1
1
1
0
1
1
1
2
Asynchronous
11 bits
1
Asynchronous w/
11 bits
Multiprocessor communication
3
Asynchronous
11 bits
3
Asynchronous w/
11 bits
Multiprocessor communication
PERIOD
12 t_CLK
4 t_CLK
Timer 1 or 2
baud rate equation
64 t_CLK (SMOD=0)
32 t_CLK (SMOD=1)
64 t_CLK (SMOD=0)
32 t_CLK (SMOD=1)
Timer 1 or 2
baud rate equation
Timer 1 or 2
baud rate equation
SM0/FE_0
Bit 7
SM1_0
Bit 6
SM2_0
Bit 5
REN_0
Bit 4
Framing Error Flag. When SMOD0 (PCON.6)=0, this bit (SM0) is used to
select the mode for serial port 0. When SMOD0 (PCON.6)=1, this bit (FE) will
be set upon detection of an invalid stop bit. When used as FE, this bit must be
cleared in software. Once the SMOD0 bit is set, modifications to this bit will not
affect the serial port mode settings. Although accessed from the same register,
internally the data for bits SM0 and FE are stored in different locations.
No alternate function.
Multiple CPU Communications. The function of this bit is dependent on the
serial port 0 mode.
Mode 0: Selects 12 t_CLK or 4 t_CLK period for synchronous serial port 0 data
transfers.
Mode 1: When set, reception is ignored (RI_0 is not set) if invalid stop bit
received.
Mode 2/3: When this bit is set, multiprocessor communications are enabled in
modes 2 and 3. This will prevent the RI_0 bit from being set, and an
interrupt being asserted, if the 9^th bit received is not 1.
Receiver Enable. This bit enable/disables the serial port 0 receiver shift register.
0 = Serial port 0 reception disabled.
1= Serial port 0 receiver enabled (modes 1, 2, 3). Initiate synchronous reception
(mode 0).
27 of 155