DS80C390_00 Datasheet, PDF (43/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
CAN 0 Interrupt Register (C0IR)
7
6
5
4
3
2
1
0
SFR A5h
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
C0IR.7-0
Bit 7-5
CAN 0 Interrupt Indicator 7-0 This register indicates the status of the
interrupt source associated with the CAN 0 module. Reading this register
after the generation of a CAN 0 Interrupt will identify the interrupt source as
shown in the table below. This register is cleared to 00h following a reset.
C0IR.7-0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
Priority
N/A
1 (highest)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 (lowest)
Interrupt Source
No Pending Interrupt
Change in the CAN 0 Status Register
Message 15
Message 1
Message 2
Message 3
Message 4
Message 5
Message 6
Message 7
Message 8
Message 9
Message 10
Message 11
Message 12
Message 13
Message 14
The C0IR value will not change unless the previous interrupt source has been
acknowledged and removed (i.e., software read of the C0S register or clearing of
the appropriate INTRQ bit), even if the new interrupt has a higher priority. If two
enabled interrupt sources become active simultaneously, the interrupt of higher
priority will be reflected in the C0IR value.
The CAN 0 interrupt source into the interrupt logic is active whenever C0IR is not
equal to 00h. Changes in the C0IR value from 00h to a non-zero state, indicate the
first interrupt source detected by the CAN module following the non-active
interrupt state. The C0IR interrupt values will remain in place until the interrupt
source is removed, independent of other higher (or lower) priority interrupts that
become active prior to clearing the currently displayed interrupt source.
When the current CAN interrupt source is cleared, C0IR will change to
reflect the next active interrupt with the highest priority. The Status Change
interrupt will be asserted if there has been a change in the Can 0 Status
Register (if enabled by the appropriate ERIE and/or STIE bit) and the CAN
Status Interrupt state is set. A message center interrupt will be indicated if the
INTRQ bit in the respective CAN Message Control Register is set.
43 of 155