DS80C390_00 Datasheet, PDF (36/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
CAN 0 Control Register (C0C)
7
6
5
4
3
2
1
0
SFR A3h ERIE
STIE
PDE SIESTA CRST AUTOB ERCS SWINT
RW-0 RW-0 RW-0 RW-0 RT-1 RW-0 RW-0 RW-1
R=Unrestricted Read, W=Unrestricted Write, T=Timed Access Write Only, -n=Value after Reset
ERIE
Bit 7
STIE
Bit 6
PDE
Bit 5
SIESTA
Bit 4
CAN 0 Error Interrupt Enable.
0 = CAN 0 Error Interrupt is disabled.
1 = Setting this bit while the C0IE bit (EIE.6) and Global Interrupt Enable
bits (IE.7) are set will generate an interrupt if the CAN 0 Bus Off
(BUSOFF) or CAN 0 Error Count Exceeded bit (CECE) bits are set.
CAN 0 Status Interrupt Enable.
0 = CAN 0 Status Interrupt is disabled.
1 = If the C0IE bit (EIE.6) is set, an interrupt will be generated if the CAN 0
Transmit Status bit (TXS), Receive Status bit (RXS) or the Wake-Up
Status bit (WKS) is set. An interrupt will also be generated if the Status
Error bits (ER2-0) changes to a non-000b or non-111b state.
CAN 0 Power Down Enable. Setting this bit places the CAN 0 module into its
lowest power mode. The module will enter Power Down mode immediately upon
setting this bit, or following the completion of the current reception, transmission,
arbitration failure, or error condition on CAN 0. Software can poll the PDE bit to
ascertain whether the microcontroller has entered Power Down mode (PDE=1) or
is waiting for a current CAN operation to complete (PDE=0) before entering
Power Down Mode.
Power Down mode is exited by clearing the PDE bit or by any reset of the
microcontroller. The CAN 0 module will resume operation after the receipt of 11
consecutive recessive bits.
The Wake-Up Status bit, WKS, is a logical OR of this bit and the SIESTA bit.
CAN 0 Siesta Mode Enable. Setting this bit places the CAN 0 module into a low
power mode. The module will enter Siesta mode immediately upon setting this
bit, or following the completion of the current reception, transmission, arbitration
failure, or error condition on CAN 0. Software can poll the SIESTA bit to
ascertain whether the microcontroller has entered Siesta mode (SIESTA =1) or is
waiting for a current CAN operation to complete (SIESTA =0) before entering
Siesta Mode.
Siesta mode is exited by clearing the Siesta bit, detecting CAN 0 bus activity, or
setting either the CRST or SWINT bits to 1. The CAN 0 module will begin
operation after the receipt of 11 consecutive recessive bits.
The Wake-Up Status bit, WKS, is a logical OR of this bit and the PDE bit.
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