DS80C390_00 Datasheet, PDF(113/155 Page) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

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DS80C390_00 Datasheet, PDF (113/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

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DS80C390 High-Speed Microcontroller Userâs Guide Supplement

One additional machine cycle is required to handle the 8 bits associated with the extension to 22-bit

addressing. The storage of the 22-bit address during an interrupt, LCALL, or ACALL instruction also

requires three bytes of stack memory as opposed to the traditional two bytes in the 16-bit address mode.

In this mode, the third byte of the PC (PC[22:16]) is not incremented when the lower 16 bits in the lower

two bytes of the PC (PC[15:0]) rolls over from FFFFh to 0000h. In the 22-bit paged address mode

PC[22:16] functions only as a storage register which is loaded by the Address Page (AP) register

whenever the processor executes either a LJMP, ACALL or LCALL instruction. PC[22:16] is stored and

retrieved from the stack with the lower 16-bit of address in PC[15:0] when stack operation is required.

Execution of DPTR-related instructions in the paged address mode is limited to the 64K byte page that is

pointed by the current content of the selected extended DPTR register. The values in the DPX and DPX1

registers are not affected when the lower 16 bits of the selected DPTR overflows or underflowed. The

execution of either the JMP @A+DPTR or the MOVC A, @A+DPTR instruction is limited to the current

64 KB page as specified by the PCX register. The contents of the DPX and DPX1 registers will not affect

the operation of either instruction.

The modification of the instructions in the 22-bit page address mode is summarized in the following

table.

INSTRUCTION CODE

MNEMONIC D7 D6 D5 D4 D3 D2 D1 D0

ACALL addr a10 a9 a8 1 0 0 0 1

a7 a6 a5 a8 a3 a2 a1 a0

HEX

Byte 1

Byte 2

BYTE

CYCLE EXPLANATION

(PC15:0)=(PC15:0)+2

(SP) = (SP) + 1

((SP)) = (PC7:0)

(SP) = (SP) + 1

((SP)) = (PC15-8)

(SP) = (SP) + 1

LCALL addr 0 0 0 1 0 0 1 0 12

a15 a14 a13 a12 a11 a10 a9 a8 Byte 2

a7 a6 a5 a5 a3 a2 a1 a0 Byte 3

((SP))=(PC23:16)

(PC10:0)=addr11

(PC23:16)=(AP7:0)

(PC15:0)=(PC15:0)+3

(SP) = (SP) + 1

((SP)) = (PC7:0)

(SP) = (SP) + 1

((SP)) = (PC15-8)

(SP) = (SP) + 1

RET

0 0 1 0 0 0 1 0 22

((SP))=(PC23:16)

(PC)=addr16

(PC23:16)=(AP7:0)

(PC23:16)=((SP))

(SP)=(SP)-1

(PC15-8)=((SP))

(SP)=(SP)-1

(PC7:0)=((SP))

(SP)=(SP)-1

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