DS80C390_00 Datasheet, PDF (153/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
SECTION 19: ARITHMETIC ACCELERATOR
The DS80C390 incorporates an arithmetic accelerator which performs 32- and 16-bit calculations while
maintaining 8051 software compatibility. Math operations are performed by sequentially loading three
special registers. The mathematical operation is determined by the sequence in which three dedicated
SFRs (MA, MB and MC) are accessed, eliminating the need for a special step to choose the operation.
The arithmetic accelerator has four functions: multiply, divide, shift right/left, and normalize. The
normalize function facilitates the conversion of 4-byte unsigned binary integers into floating point format.
An integral 40-bit accumulator, described later, supports multiply-and-add and divide-and-add operations.
The following table shows the operations supported by the math accelerator and their time of execution.
ARITHMETIC ACCELERATOR EXECUTION TIMES Table 19-1
Operation
Result
32-bit/16-bit divide
32-bit quotient, 16-bit remainder
16-bit/16-bit divide
16-bit quotient, 16-bit remainder
16-bit/16-bit multiply
32-bit product
32-bit shift left/right
32-bit result
32-bit normalize
32-bit mantissa, 5 bit exponent
Execution Time
36 t_CLCL
24 t_CLCL
24 t_CLCL
36 t_CLCL
36 t_CLCL
The following is a brief summary of the bits and registers used in conjunction with arithmetic acceleration
operations. Please consult the SFR listing in Section 4for a complete description of all these registers.
LSHIFT ^{Left Shift. This bit determines whether shift operations proceed from LSb to MSb or}
MCNT0.7 ^{vice versa.}
CSE
Circular Shift Enable. This bit determines whether shift operations will wrap
MCNT0.6 between the LSb and MSb.
SCE
Shift Carry Enable. This bit determines whether the arithmetic accelerator carry bit
MCNT0.5 is included in the shift process.
MAS4-0
MCNT0.4-
0.
Multiplier Register Shift Bits. When performing a shift operation, these bits
determine how many shifts to perform. Following a normalize operation, these bits
will contain indicate the number shifts performed.
MST
Multiply/Accumulate Status Flag. This bit serves as a busy flag for the arithmetic
MCNT1.7 accumulator operations.
MOF
Multiply Overflow Flag. This bit is set when a divide by zero or when the result of
MCNT1.6 a calculation exceeds FFFFh.
SCB
MCNT1.5
Shift Carry Bit. This bit serves as the carry bit during arithmetic accelerator shift
operations when SCE=1. This bit must be cleared (or set) via software as desired
before each new shift operation.
CLM
Clear Accelerator Registers. Setting this bit clears the MA, MB, and MC registers.
MCNT1.4
MA
MA.7-0
Multiplier A Register. This register is used as both a source and result register for
various arithmetic accelerator functions.
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