DS80C390_00 Datasheet, PDF (124/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
CAN Bus Timing Register 1 (CnBT1)
MOVX
Address¹
7
6
5
4
3
2
1
0
xxxx05h SMP TSEG26 TSEG25 TSEG24 TSEG13 TSEG12 TSEG11 TSEG10
SMP
Bit 7
TSEG26-24
Bits 6-4
TSEG13-10
Bits 3-0
CAN Sampling Rate. The Sampling Rate (SMP) bit determines the number of
samples to be taken during each receive bit time. Programming SMP = 0 will take
only one sample during each bit time. Programming SMP = 1 will direct the CAN
logic to take three samples during each bit time, and to use a majority voting
circuit to determine the final bit value. When SMP is set to a 1, two additional t_qu
clock cycles are be added to Time Segment One. SMP should not be set to one
when the Baud Rate Prescale Value (BRPV) is less than 4. This bit can only be
modified during a software initialization (SWINT=1).
CAN Time Segment 2 Select. The eight states defined by the TSEG26 -
TSEG24 bits determine the number of clock cycles in the Phase Segment 2
portion of the nominal bit time, which occurs after the sample time. These bits
can only be modified during a software initialization (SWINT=1).
TSEG26
0
TSEG25
0
TSEG24
0
Time Segment Two Length
(Number in parenthesis is TS2_LEN value used in
bit timing calculations)
Invalid
0
0
1
2 t_qu (2)
0
1
0
3 t_qu (3)
.
.
.
.
1
1
0
7 t_qu (7)
1
1
1
8 t_qu (8)
CAN Time Segment 1 Select. The sixteen states defined by the TSEG13 -
TSEG10 bits determine the number of clock cycles in the Phase Segment 1
portion of the nominal bit time, which occurs before the sample time. These bits
can only be modified during a software initialization (SWINT=1).
TSEG13
0
0
0
.
1
1
TSEG12
0
0
0
.
1
1
TSEG11
0
0
1
.
1
1
TSEG10
0
1
0
.
0
1
Time Segment One Length
(Number in parenthesis is TS1_LEN
value used in bit timing calculations)
Invalid
2 t_qu (2)
3 t_qu (3)
.
15 t_qu (15)
16 t_qu (16)
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