DS80C390_00 Datasheet, PDF (71/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
Multiplier Control Register One (MCNT1)
7
6
5
4
3
2
1
0
SFR D2h MST MOF
SCB
CLM
1
1
1
1
RW-0
R-0
RW-0 RW-0
R-1
R-1
R-1
R-1
R=Unrestricted Read, W=Unrestricted Read, -n=Value after Reset
MST
Bit 7
MOF
Bit 6
SCB
Bit 5
CLM
Bit 4
Bit 3-0
Multiply/Accumulate Status Flag. The MST bit serves as a busy flag for the
multiplier/accumulate hardware. The bit is set automatically when the processor
begins loading data into the MA or MB register, and will remain set until the
assigned task is completed. MST is automatically cleared by the
multiplier/accumulate hardware once an assigned task is completed and the
results are ready for the processor to read. MST=0 also indicates that the
accelerator has been initialized and can be loaded with new values. Clearing this
bit via software from a previous high state will terminate the current operation
and initialize the multiplier, allowing the immediate loading of new data into MA
and/or MB to perform a new calculation.
Multiply Overflow Flag. The MOF flag bit is cleared following a either a
system reset or the initialization of the accelerator. The MOF bit is automatically
set when the accelerator detects a divide by zero, or when the result of the
calculation is larger than FFFFh.
Shift Carry Bit. The SCB bit is used as a carry bit for shift operation when SCE
bit is set to 1. Note that the SCB will not be cleared at the beginning of a new
operation and must be cleared by a write to this bit or a system reset.
Clear Accelerator Registers. Writing a one to this bit will clear the MA, MB,
and MC registers. Reading this bit will always return a logic 0.
Reserved
Multiplier A Register (MA)
7
6
SFR D3h
RW-0 RW-0
5
RW-0
4
RW-0
3
RW-0
2
RW-0
1
RW-0
0
RW-0
R=Unrestricted Read, W=Unrestricted Read, -n=Value after Reset
Bits 7-0
Multiplier A Register. The MA Register is used as both a source and result
register for various arithmetic accelerator functions. When in the source mode it
is loaded with the numerator for divide operations and the multiplicand when
performing multiply operations. The MA register also holds the quotient of the
divide operations, multiply product, shift results, and mantissa of the normalize
function.
The MA register can receive or hold up to a 32-bit result, accessed via a series of
sequential writes to or reads from the register. Details of the sequencing are
explained in the arithmetic accelerator section of the User’s Guide.
71 of 155