DS80C390_00 Datasheet, PDF (29/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
Address Page Register (AP)
7
6
5
4
3
2
1
0
SFR 9Ch
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
AP.7-0
Bits 7-0
Address Page Register. The AP Register (AP) supports extended program and
data addressing (>64KB) capabilities in the 22-bit paged addressing mode (AM1,
AM0 = 01b), and is fully compatible with the original 8052 16-bit addressing
mode. When executing LJMP, ACALL, or LCALL instructions in paged
addressing mode, the microcontroller automatically loads bits 23:16 of the
program counter with the contents of the AP register to calculate the new CALL
or JMP address. The AP register affects only the previous instruction, and is not
incremented during a program counter rollover from FFFFh to 0000h. This
register is a general purpose SFR when not operating in 22-bit paged mode.
Executing interrupts while in 22-bit paged addressing mode pushes the three
bytes of the program counter onto the stack, but not the AP register itself. The AP
register should be saved at the beginning of the ISR if it will be modified inside
the ISR. Following the execution of a RETI instruction, the processor will
automatically reload the entire 24 value of the PC with the original address from
the stack, again leaving the contents of the AP register unchanged.
Address Control Register (ACON)
7
6
5
4
SFR 9Dh 1
1
1
1
R-1
R-1
R-1
R-1
3
2
1
0
1
SA
AM1
AM0
R-1
RT-0
RT-0
RT-0
R=Unrestricted Read, T=Timed Access Write Only, -n=Value after Reset
Bits 7-3
Reserved
SA
Extended Stack Address Mode Enable. This bit can only be modified via the
Bit 2
Timed Access procedure.
0 = All instructions will utilize the traditional 8-bit 8051 stack pointer (SP;81h).
1 = All instructions will utilize the 10-bit stack pointer formed by concatenating
the 2 least significant bits of the ESP register with the SP register. Lower 1
KB of internal MOVX memory is used as the stack when this bit is set. This
bit cannot be set while IDM1:IDM0=11b.
AM1, AM0
Bits 1-0
Address Mode Control bits. These bits establish the addressing mode for the
device. These bits can only be modified via the Timed Access procedure.
AM1 AM0
0
0
Addressing Mode
16-bit Addressing Mode
0
1
22-bit Paged Addressing Mode
1
x
22-bit Contiguous Addressing Mode
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