DS80C390_00 Datasheet, PDF (112/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
ADDENDUM TO SECTION 16: INSTRUCTION SET DETAILS
The DS80C390 supports one of three different address modes, selected via the AM1 and AM0 bits in the
ACON register. The processor operates in either the traditional 16-bit address mode, 22-bit paged address
mode or in a 22-bit contiguous address mode. When operating in the 16-bit addressing mode (AM1, AM0
= 00b), all instruction cycle timing and byte counts will be identical to the 8051 family. Use of the 24-bit
paged address mode is binary code-compliant with the traditional (16-bit) 8051 compilers, but allows for
up to 4M bytes of program and 4M bytes of data memory to be supported via a new Address Page SFR
which supports an internal bank switch mechanism. The 22-bit contiguous mode requires a compiler that
supports contiguous program flow over the entire 22-bit address range via the addition of an operand
and/or cycles to eight basic instructions.
16-BIT (8051 STANDARD) ADDRESSING MODE
This addressing mode is identical to that used by the 8051 family and most members of the High-Speed
Microcontroller. The microcontroller defaults to this mode following a reset. This mode can also be used
to run code compiled or assembled for the 22-bit contiguous mode, as long as the following four
instructions are not executed:
MOV DPTR, #data24,
ACALL addr19
LCALL addr24
LJMP addr24
These four branch instructions are the only instructions that will cause the compiler to generate additional
operands relative to the 16-bit addressing mode. Note that the number of cycles per instruction may
appear different from other instructions, but this is ignored by most assemblers or compilers and as such
does not pose a problem with the binary output.
By selecting the 24-bit contiguous mode prior using any one of these four branch instructions, it is
possible to run 24-bit contiguous compiled code in the default 16-bit address configuration. Once the
AM0 and AM1 bits are set to the 24-bit contiguous address mode, the instructions seen above will
execute properly. When the 24-bit paged address mode is selected, all instructions complied under the
traditional 16-bit address mode will execute normally at any point in code.
22-BIT PAGED ADDRESSING MODE
The DS80C390 incorporates an internal 8-bit Address Page Register (AP), an 8-bit extended DPTR
Register (DPX), and an 8-bit extended DPTR1 Register (DPX1) as hardware support for 22-bit
addressing in the paged address mode (AM1, AM0 = 01b). The only difference found in executing code
in the traditional 16-bit mode and the 22-bit paged mode is the additional of one machine cycle when
executing the ACALL, LCALL, RET and RETI instructions as well as when the hardware processes an
interrupt.
The DS80C390 supports interrupts from any location in the 22-bit address field. When an interrupt
request is acknowledged, the current contents of the 22-bit Program Counter (PC) is pushed onto the
stack, and the page value (00h) and the lower 16-bit address of the interrupt vector is then written to the
PC before the execution of the LCALL. This means that all interrupt vectors are fetched from address
0000xxh, rather than the current page as defined by the AP register. The RETI instruction will pop the
three address bytes from the stack, and will restore these bytes back to the PC at the conclusion of the
interrupt service routine. Interrupt service routines that branch over page boundaries must save the current
contents of AP before altering the AP register, as it is not automatically saved on the stack. This
mechanism will support up to three levels of nesting for interrupts.
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