DS80C390_00 Datasheet, PDF (58/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
Power Management Register (PMR)
7
6
5
4
3
2
1
0
SFR C4h CD1
CD0
SWB
CTM 4X/ 2X ALEOFF
1
1
R*-1
R*-0 RW-0 R*-0
R*-0 RW-0
R-1
R-1
R=Unrestricted Read, W= Unrestricted Write, *= See description below, -n=Value after Reset
CD1, CD0
Bits 7-6
Clock Divide Control 1-0. These bits select the number of crystal oscillator
clocks required to generate one machine cycle. Switching between modes
requires a transition through the divide by 4 mode (CD1, CD0=01). For example,
to go from 1 to 1024 clocks per machine cycle the device must first go from 1 to
4 clocks per cycle, and then from 4 to 1024 clocks per cycle. Attempts to perform
an invalid transition will be ignored. The setting of these bits will effect the
timers and serial ports as shown below.
Attempts to change these bits to the frequency multiplier (1 or 2 clocks per cycle)
setting will fail when running from the internal ring oscillator. In addition, it is
not possible to change these bits to the 1024 clocks per machine cycle setting
while the switchback enable bit (SWB) is set and any of the switchback sources
(external interrupts or serial port transmit or receive activity) are active.
CD1:0 4X/ 2X
00
1
00
0
01
x
10
x
11
x
OSCILLATOR OSC CYCLES OSC CYCLES OSC CYCLES PER
CYCLES PER PER TIMER 0/1/2 PER TIMER 2 SERIAL PORT CLK,
MACHINE.
CLOCK.
CLK, BAUD
MODE 0
CYCLE
RATE GEN.
TxM=0 TxM=1
SM2=0 SM2=1
1
2
4
1024
12
12
12
3072
1
2
4
1024
2
2
Reserved
2
512
3
6
12
3072
1
2
4
1024
OSC CYCLES PER
SERIAL PORT CLK,
MODE 2
SMOD=0 SMOD=1
64
32
64
32
64
32
64
32
SWB
Bit 5
Switchback Enable. This bit allows an enabled external interrupt or serial port
activity to force the Clock Divide Control bits to the divide by 4 state (10) when
the microcontroller is in the divide by 1024 state. Upon internal
acknowledgement of an external interrupt, the device will switch modes at the
start of the jump to the interrupt service routine. Note that this means that an
external interrupt must actually be recognized (i.e., be enabled and not masked by
higher priority interrupts) for the switchback to occur. For serial port reception,
the switch occurs at the start of the instructions following the falling edge of the
start bit.
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