DS80C390_00 Datasheet, PDF (137/155 Pages) Dallas Semiconductor – High-Speed Microcontroller User’s Guide Supplement

DS80C390 High-Speed Microcontroller User’s Guide Supplement
Initializing the CAN controllers
Software initialization of each CAN controller begins with the setting of the Software Initialization bit
(SWINT) in the appropriate CAN Control SFR Register. When SWINT=1, the respective CAN module is
disabled and the corresponding CAN transmit output will be placed in a recessive state. This in turn
allows the microcontroller to write information into the CAN MOVX SRAM Control/Status/Mask
registers without the possibility of corrupting data transmissions or receptions in progress. Setting
SWINT will not clear the receive and transmit error counters, but will allow the microcontroller to write a
common value to both error counters via the CAN Transmit Error SFR Register. Consult the description
of the SWINT bit for specifics of the software initialization process.
All CAN registers located in the SFR memory map, with the exception of the CAN 0 and CAN 1 Control
Registers, are cleared to a 00 Hex following a system Reset. The CAN 0 and CAN 1 Control Registers,
are set to 0B Hex following a system Reset. CAN registers located in the MOVX memory map are
indeterminate following a system Reset. A system Reset also clears both the receive and transmit error
counters in the CAN controllers, takes the CAN processors off line, and sets the SWINT bit in the CAN
0/1 Control Register.
Following a reset, the following general registers must be initialized for proper operation of the CAN
modules. These registers are in addition to specific registers associated with mask, format, or specific
message centers.
Register
Significance
P5CNT (SFR A2h)
C0_I/O (P5CNT.3) must be set to enable CAN 0 pins P5.1 and P5.0.
C1_I/O (P5CNT.4) must be set to enable CAN 1 pins P5.2 and P5.3
C0BT0, C0BT1
These MOVX SRAM control registers must be set to configure CAN 0
C1BT0, C1BT1
(C0BT0, C0BT1) or CAN 1 (C1BT0, C1BT1) bus timing. The exact
(MOVX SRAM xxxx04-5) values are dependent on the network configuration and environment.
COR (SFR CEh)
C0BPR7-6 (COR.4-3) must be configured as part of the CAN 0 bus timing
C1BPR7-6 (COR.6-5) must be configured as part of the CAN 1 bus timing
CAN Interrupts
Each CAN processor is assigned one individual interrupt and one common CAN Bus Activity Interrupt
which are globally enabled or disabled by the EA bit in the IE SFR register. The CAN 0/1 interrupt is
generated by either a receive/transmit acknowledgment from one of the fifteen message centers or an
error condition which results in a change in the CAN 0/1 Status Register. These interrupts are enabled via
the C0IE or C1IE bit (CAN 0 or CAN 1) in the EIE register. The third CAN related interrupt is common
to both CAN systems and is supplied to detect CAN bus activity on either CAN input pin. This interrupt
is termed the CAN Bus Activity Interrupt, operates independent of the CAN processor, and is only
available if one or both of the CAN processors have been connected to the respective Port 5 pins (via
C0_I/O and/or C1_I/O in the Port 5 Control SFR).
CAN 0/1 receive/transmit interrupt sources are derived from a successful transmit or receive of data
within one of the fifteen message centers as determined by the INTRQ bit in the associated CAN 0/1
Message (1-15) Control Register. Each message center (1-15) also provides separate receive and transmit
interrupt enables via the ETI and ERI bits in the respective CAN 0/1 Message (1-15) Control Register.
This allows each message center to be programmed to issue an interrupt request as per the application
requirements of the message center. Each source is determined through the use of the CAN 0/1 Interrupt
137 of 155