EP3SE80F780I4N Datasheet, PDF (99/341 Pages) Altera Corporation – Chapter Revision Dates

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–89
Table 1–57. EP3SL70 Column Pins Output Timing Parameters (Part 4 of 4)
I/O Standard
Clock
Fast Model
Industrial Commercial
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
8mA
GCLK
PLL
t_co
3.034
3.032
3.258
3.256
4.627 5.034 5.551 5.411 5.629 5.162 5.680 5.542 5.699 ns
4.625 5.032 5.549 5.409 5.627 5.160 5.677 5.539 5.696 ns
DIFFERENTIAL
GCLK t_co
2.5-V SSTL
CLASS I
10mA _GCLK
PLL
t_co
3.036
3.036
3.258
3.259
4.617 5.022 5.537 5.397 5.615 5.149 5.664 5.526 5.683 ns
4.625 5.032 5.549 5.409 5.627 5.160 5.677 5.539 5.696 ns
GCLK t_co
12mA _GCLK
PLL
t_co
3.052
3.052
3.276
3.276
4.641 5.047 5.563 5.423 5.641 5.175 5.690 5.552 5.709 ns
4.641 5.047 5.563 5.423 5.641 5.175 5.690 5.552 5.709 ns
DIFFERENTIAL
GCLK t_co
2.5-V SSTL
CLASS II
16mA _GCLK
PLL
t_co
3.042
3.035
3.266
3.258
4.631 5.037 5.553 5.413 5.631 5.165 5.681 5.543 5.700 ns
4.617 5.022 5.537 5.397 5.615 5.149 5.664 5.526 5.683 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2