EP3SE80F780I4N Datasheet, PDF (156/341 Pages) Altera Corporation – Chapter Revision Dates

1–146
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–79 and Table 1–80 list the EP3SL150 regional clock (RCLK) adder values that
must be added to the GCLK values. Use these adder values to determine I/O timing
when the I/O pin is driven using the regional clock. This applies to all I/O standards
supported by Stratix III devices.
Table 1–79 lists the EP3SL150 column pin delay adders when using the regional clock.
Table 1–79. EP3SL150 Column Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
Industrial Commercial
0.198
2.453
-0.374
-2.017
0.152
2.426
-0.152
-1.798
C2
C3
V_CCL=
1.1 V
V_CCL=
1.1 V
0.22 0.258
3.654 4.098
-0.216 -0.232
-2.68 -2.859
C4
V_CCL=
1.1 V
0.27
4.422
-0.248
-3.011
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
0.262 0.393
4.224 4.664
-0.227 -0.367
-2.872 -2.715
I3
V_CCL=
1.1 V
0.244
4.106
-0.11
-2.714
I4
V_CCL=
1.1 V
0.271
4.447
-0.127
-3.082
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
0.261 0.495
4.101 4.707
-0.106 -0.303
-2.791 -2.766
Units
ns
ns
ns
ns
Table 1–80 lists the EP3SL150 row pin delay adders when using the regional clock.
Table 1–80. EP3SL150 Row Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
Industrial Commercial
0.107
0.074
-0.093
-0.063
0.115
0.075
-0.103
-0.065
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
0.164 0.165 0.167 0.165 0.285 0.158 0.159 0.158 0.29 ns
0.116 0.123 0.129 0.126 0.218 0.114 0.118 0.114 0.223 ns
-0.137 -0.136 -0.133 -0.134 -0.257 -0.125 -0.121 -0.122 -0.261 ns
-0.097 -0.102 -0.103 -0.102 -0.198 -0.088 -0.089 -0.088 -0.202 ns
EP3SL200 I/O Timing Parameters
Table 1–81 through Table 1–84 list the maximum I/O timing parameters for EP3SL200
devices for single-ended I/O standards.
Table 1–81 lists the EP3SL200 column pins input timing parameters for single-ended
I/O standards.
Table 1–81. EP3SL200 Column Pins Input Timing Parameters (Part 1 of 4)
I/O
Standard
3.3-V
LVTTL
3.3-V
LVCMOS
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
-1.137
1.285
-1.465
1.778
-1.137
1.285
-1.465
1.778
-1.173
1.319
-1.465
1.778
-1.173
1.319
-1.465
1.778
-1.810 -1.775 -2.002 -1.934 -2.482 -1.775 -2.002 -1.934 -2.482 ns
2.032 2.008 2.259 2.177 2.724 2.008 2.259 2.177 2.724 ns
-2.238 -2.271 -2.558 -2.477 -2.997 -2.271 -2.558 -2.477 -2.997 ns
2.727 2.776 3.113 3.000 3.543 2.776 3.113 3.000 3.543 ns
-1.810 -1.775 -2.002 -1.934 -2.482 -1.775 -2.002 -1.934 -2.482 ns
2.032 2.008 2.259 2.177 2.724 2.008 2.259 2.177 2.724 ns
-2.238 -2.271 -2.558 -2.477 -2.997 -2.271 -2.558 -2.477 -2.997 ns
2.727 2.776 3.113 3.000 3.543 2.776 3.113 3.000 3.543 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation