EP3SE80F780I4N Datasheet, PDF (152/341 Pages) Altera Corporation – Chapter Revision Dates

1–142
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–77. EP3SL150 Column Pins Output Timing Parameters (Part 4 of 4)
I/O Standard
Clock
Fast Model
Industrial Commercial
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
8mA
GCLK
PLL
t_co
DIFFERENTIAL
2.5-V SSTL
GCLK t_co
CLASS I
10mA _GCLK
PLL
t_co
3.123
1.331
3.123
1.331
3.360
1.510
3.360
1.510
4.753 5.150 5.662 5.523 5.807 5.274 5.784 5.648 5.881 ns
1.951 2.049 2.264 2.275 2.302 2.155 2.371 2.381 2.289 ns
4.753 5.150 5.662 5.523 5.807 5.274 5.784 5.648 5.881 ns
1.951 2.049 2.264 2.275 2.302 2.155 2.371 2.381 2.289 ns
GCLK t_co
12mA _GCLK
PLL
t_co
3.113
1.321
3.350
1.500
4.743 5.140 5.652 5.513 5.797 5.264 5.775 5.639 5.872 ns
1.941 2.039 2.254 2.265 2.292 2.145 2.362 2.372 2.280 ns
DIFFERENTIAL
GCLK t_co
2.5-V SSTL
CLASS II
16mA _GCLK
PLL
t_co
3.106
1.314
3.342
1.492
4.729 5.125 5.636 5.497 5.781 5.248 5.758 5.622 5.855 ns
1.927 2.024 2.238 2.249 2.276 2.129 2.345 2.355 2.263 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation