EP3SE80F780I4N Datasheet, PDF (298/341 Pages) Altera Corporation – Chapter Revision Dates

1–288
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–133 lists the EP3SE260 column pins output timing parameters for
single-ended I/O standards.
Table 1–133. EP3SE260 Column Pins Output Timing Parameters (Part 1 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
4mA _GCLK
PLL ^tco
3.644
4.087
3.677
4.076
5.302 5.460 6.139 5.837 6.259 5.460 6.139 5.837 6.259 ns
5.937 6.144 6.701 6.529 7.188 6.144 6.701 6.529 7.188 ns
3.3-V
LVTTL
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.577
4.020
3.491
3.934
3.610
4.009
3.524
3.923
5.193 5.349 5.969 5.724 6.146 5.349 5.969 5.724 6.146 ns
5.828 6.033 6.588 6.416 7.018 6.033 6.588 6.416 7.018 ns
5.089 5.250 5.817 5.632 6.054 5.250 5.817 5.632 6.054 ns
5.724 5.934 6.496 6.324 6.866 5.934 6.496 6.324 6.866 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.484
3.927
3.517
3.916
5.072 5.222 5.792 5.591 6.013 5.222 5.792 5.591 6.013 ns
5.707 5.906 6.455 6.283 6.841 5.906 6.455 6.283 6.841 ns
GCLK t_co
4mA _GCLK
PLL ^tco
3.650
4.093
3.683
4.082
5.306 5.465 6.153 5.844 6.266 5.465 6.153 5.844 6.266 ns
5.941 6.149 6.708 6.536 7.202 6.149 6.708 6.536 7.202 ns
3.3-V
LVCMOS
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.495
3.938
3.502
3.945
3.528
3.927
3.535
3.934
5.099 5.267 5.823 5.643 6.065 5.267 5.823 5.643 6.065 ns
5.734 5.951 6.507 6.335 6.872 5.951 6.507 6.335 6.872 ns
5.093 5.246 5.792 5.617 6.039 5.246 5.792 5.617 6.039 ns
5.728 5.930 6.481 6.309 6.841 5.930 6.481 6.309 6.841 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.486
3.929
3.519
3.918
5.071 5.221 5.735 5.588 6.010 5.221 5.735 5.588 6.010 ns
5.706 5.905 6.452 6.280 6.784 5.905 6.452 6.280 6.784 ns
GCLK t_co
4mA _GCLK
PLL ^tco
3.608
4.051
3.641
4.040
5.269 5.428 6.104 5.804 6.226 5.428 6.104 5.804 6.226 ns
5.904 6.112 6.668 6.496 7.153 6.112 6.668 6.496 7.153 ns
3.0-V
LVTTL
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.497
3.940
3.461
3.904
3.530
3.929
3.494
3.893
5.139 5.294 5.942 5.668 6.088 5.294 5.942 5.668 6.088 ns
5.774 5.978 6.531 6.360 6.990 5.978 6.531 6.360 6.990 ns
5.076 5.225 5.840 5.594 6.014 5.225 5.840 5.594 6.014 ns
5.711 5.909 6.457 6.286 6.888 5.909 6.457 6.286 6.888 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.443
3.886
3.476
3.875
5.047 5.197 5.790 5.564 5.986 5.197 5.790 5.564 5.986 ns
5.682 5.881 6.428 6.256 6.838 5.881 6.428 6.256 6.838 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation