EP3SE80F780I4N Datasheet, PDF (46/341 Pages) Altera Corporation – Chapter Revision Dates

1–36
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–37. Output Timing Measurement Methodology for Output Pins (Part 3 of 3)
I/O Standard
MINI-LVDS_E_1R
Loading and Termination
R_S
R_D
R_T
R_P
V_CCIO
V_CCPD
V_CC
— 100 — 120 2.325 2.325 1.02
MINI-LVDS_E_3R
120 100 — 170 2.325 2.325 1.02
RSDS_E_1R
— 100 — 120 2.325 2.325 1.02
RSDS_E_3R
120 100 — 170 2.325 2.325 1.02
Notes to Table 1–37:
(1) Hyper transport is not supported by Stratix III devices.
(2) LVPECL outputs are not supported by Stratix III devices.
(3) You can change the Quartus II timing conditions using the Advanced I/O Timing feature.
(4) V_CC is nominally 1.1 V less 50 mV (1.05 V).
(5) Terminated I/O standards require an additional 30 mV IR drop on V_CC (1.02 V).
(6) Terminated I/O standards require an additional 50 mV IR drop on V_CCIO and V_CCPD.
Measurement
Point
V_TT
C_L (pF)
—
0
—
0
—
0
—
0
V_MEAS (v)
1.1625
1.1625
1.1625
1.1625
I/O Default Capacitive Loading
Table 1–38 lists the default capacitive loading of various I/O standards.
Table 1–38. Default Loading of Various I/O Standards for Stratix III Devices (Part 1 of 2)
I/O Standard
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVTTL/LVCMOS
3.0-V PCI
3.0-V PCI-X
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.2-V HSTL
Differential SSTL-2 CLASS I
Differential SSTL-2 CLASS II
Differential SSTL-18 CLASS I
Capacitive
Load
Unit
0
pF
0
pF
0
pF
0
pF
0
pF
0
pF
0
pF
10
pF
10
pF
0
pF
0
pF
0
pF
0
pF
0
pF
0
pF
0
pF
0
pF
0
pF
0
pF
0
pF
0
pF
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation