EP3SE80F780I4N Datasheet, PDF (88/341 Pages) Altera Corporation – Chapter Revision Dates

1–78
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–54 lists the EP3SL70 row pins output timing parameters for single-ended I/O
standards.
Table 1–54. EP3SL70 Row Pins Output Timing Parameters (Part 1 of 4)
I/O
Standard
4mA
3.3-V
LVTTL
8mA
12mA
4mA
3.3-V
LVCMOS
8mA
4mA
3.0-V
LVTTL
8mA
12mA
4mA
3.0-V
LVCMOS
8mA
4mA
2.5 V
8mA
12mA
Clock
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
GCLK
PLL
t_co
Fast Model
Industrial Commercial
3.182
3.424
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
4.767 5.163 5.668 5.532 5.739 5.293 5.802 5.667 5.813 ns
1.474
1.669 2.054 2.135 2.377 2.393 2.266 2.251 2.501 2.515 2.258 ns
3.089
3.319 4.637 5.025 5.524 5.388 5.595 5.152 5.653 5.518 5.664 ns
1.408
1.598 1.944 2.023 2.233 2.249 2.152 2.138 2.352 2.366 2.142 ns
2.990
3.213 4.518 4.902 5.396 5.260 5.467 5.025 5.521 5.386 5.532 ns
1.329
1.509 1.838 1.923 2.119 2.138 2.056 2.039 2.235 2.252 2.043 ns
3.192
3.428 4.775 5.168 5.673 5.537 5.744 5.299 5.807 5.672 5.818 ns
1.476
1.676 2.058 2.140 2.382 2.398 2.275 2.259 2.506 2.520 2.270 ns
2.994
3.219 4.524 4.908 5.402 5.266 5.473 5.031 5.528 5.393 5.539 ns
1.333
1.513 1.849 1.938 2.129 2.148 2.066 2.051 2.244 2.261 2.052 ns
3.136
3.370 4.719 5.116 5.625 5.489 5.696 5.250 5.760 5.625 5.771 ns
1.435
1.630 2.021 2.103 2.334 2.350 2.232 2.219 2.459 2.473 2.224 ns
3.011
3.243 4.566 4.957 5.461 5.325 5.532 5.088 5.596 5.460 5.606 ns
1.334
1.518 1.884 1.961 2.170 2.186 2.087 2.077 2.295 2.308 2.078 ns
2.972
3.192 4.484 4.874 5.373 5.237 5.444 5.002 5.503 5.367 5.513 ns
1.297
1.480 1.824 1.896 2.082 2.099 2.017 2.009 2.202 2.215 2.005 ns
3.050
3.289 4.613 5.009 5.514 5.378 5.585 5.142 5.649 5.513 5.659 ns
1.356
1.542 1.919 1.996 2.223 2.239 2.123 2.111 2.348 2.361 2.114 ns
2.950
3.170 4.449 4.835 5.334 5.198 5.405 4.962 5.463 5.327 5.473 ns
1.284
1.464 1.796 1.867 2.052 2.071 1.989 1.979 2.169 2.185 1.976 ns
3.162
3.406 4.851 5.270 5.797 5.661 5.868 5.410 5.939 5.803 5.949 ns
1.461
1.667 2.129 2.229 2.506 2.522 2.377 2.351 2.638 2.651 2.376 ns
3.052
3.307 4.696 5.107 5.627 5.491 5.698 5.243 5.765 5.629 5.775 ns
1.376
1.564 2.005 2.094 2.336 2.352 2.235 2.214 2.464 2.477 2.231 ns
3.006
3.231 4.585 4.988 5.501 5.365 5.572 5.120 5.635 5.499 5.645 ns
1.319
1.520 1.921 2.008 2.210 2.226 2.144 2.125 2.334 2.347 2.137 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation