EP3SE80F780I4N Datasheet, PDF (61/341 Pages) Altera Corporation – Chapter Revision Dates

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–51
Table 1–44 lists the EP3SL50 row pins output timing parameters for single-ended I/O
standards.
Table 1–44. EP3SL50 Row Pins output Timing Parameters (Part 1 of 4)
I/O
Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
V_CCL=
1.1 V 0.9 V
Units
4mA
GCLK t_co
GCLK
PLL
t_co
3.3-V
LVTTL
8mA
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
12mA
GCLK
PLL
t_co
4mA
3.3-V
LVCMOS
8mA
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
GCLK
PLL
t_co
3.0-V
LVTTL
4mA
8mA
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
12mA
GCLK
PLL
t_co
GCLK t_co
3.0-V
LVCMOS
4mA
GCLK
PLL
t_co
GCLK t_co
8mA
GCLK
PLL
t_co
4mA
GCLK t_co
GCLK
PLL
t_co
2.5 V
8mA
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
12mA
GCLK
PLL
t_co
3.197
1.482
3.104
1.415
3.014
1.336
3.207
1.492
3.018
1.340
3.151
1.442
3.026
1.341
2.987
1.304
3.065
1.363
2.969
1.291
3.177
1.468
3.067
1.383
3.021
1.326
3.438
1.677
3.333
1.606
3.233
1.517
3.442
1.684
3.237
1.521
3.384
1.638
3.257
1.526
3.206
1.488
3.303
1.550
3.188
1.472
3.420
1.675
3.321
1.572
3.245
1.528
4.781 5.176 5.684 5.549 5.751 5.305 5.818 5.682 5.828 ns
2.061 2.175 2.372 2.388 2.308 2.295 2.495 2.512 2.303 ns
4.651 5.038 5.540 5.405 5.607 5.164 5.669 5.533 5.679 ns
1.951 2.037 2.228 2.244 2.164 2.154 2.346 2.363 2.154 ns
4.532 4.915 5.412 5.277 5.479 5.037 5.537 5.401 5.547 ns
1.845 1.930 2.100 2.116 2.036 2.046 2.214 2.260 2.022 ns
4.789 5.181 5.689 5.554 5.756 5.311 5.823 5.687 5.833 ns
2.065 2.180 2.377 2.393 2.313 2.301 2.500 2.517 2.308 ns
4.538 4.921 5.418 5.283 5.485 5.043 5.544 5.408 5.554 ns
1.856 1.945 2.106 2.122 2.042 2.058 2.221 2.269 2.029 ns
4.733 5.129 5.641 5.506 5.708 5.262 5.776 5.640 5.786 ns
2.028 2.128 2.329 2.345 2.265 2.252 2.453 2.470 2.261 ns
4.580 4.970 5.477 5.342 5.544 5.100 5.612 5.475 5.621 ns
1.891 1.969 2.165 2.181 2.101 2.090 2.289 2.305 2.096 ns
4.498 4.887 5.389 5.254 5.456 5.014 5.519 5.382 5.528 ns
1.831 1.903 2.077 2.093 2.013 2.016 2.196 2.222 2.003 ns
4.627 5.022 5.530 5.395 5.597 5.154 5.665 5.528 5.674 ns
1.926 2.021 2.218 2.234 2.154 2.144 2.342 2.358 2.149 ns
4.463 4.848 5.350 5.215 5.417 4.974 5.479 5.342 5.488 ns
1.803 1.874 2.038 2.054 1.974 1.986 2.156 2.193 1.963 ns
4.865 5.283 5.813 5.678 5.880 5.422 5.955 5.818 5.964 ns
2.136 2.282 2.501 2.517 2.437 2.412 2.632 2.648 2.439 ns
4.710 5.120 5.643 5.508 5.710 5.255 5.781 5.644 5.790 ns
2.012 2.119 2.331 2.347 2.267 2.245 2.458 2.474 2.265 ns
4.599 5.001 5.517 5.382 5.584 5.132 5.651 5.514 5.660 ns
1.928 2.015 2.205 2.221 2.141 2.132 2.328 2.354 2.135 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2