EP3SE80F780I4N Datasheet, PDF (129/341 Pages) Altera Corporation – Chapter Revision Dates

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–119
Table 1–70 lists the EP3SL110 row pin delay adders when using the regional clock.
Table 1–70. EP3SL110 Row Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
Industrial Commercial
0.086
0.075
-0.072
-0.063
0.109
0.075
-0.097
-0.065
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
0.158 0.16 0.161 0.159 0.281 0.137 0.153 0.153 0.285 ns
0.117 0.123 0.129 0.125 0.222 0.113 0.118 0.114 0.226 ns
-0.137 -0.135 -0.116 -0.134 -0.24 -0.11 -0.104 -0.124 -0.244 ns
-0.097 -0.1 -0.104 -0.101 -0.198 -0.088 -0.09 -0.088 -0.201 ns
EP3SL150 I/O Timing Parameters
Table 1–71 through Table 1–74 list the maximum I/O timing parameters for EP3SL150
devices for single-ended I/O standards.
Table 1–71 lists the EP3SL150 column pins input timing parameters for single-ended
I/O standards.
Table 1–71. EP3SL150 Column Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
GCLK ^tsu
t_h
3.3-V LVTTL
GCLK ^tsu
PLL _th
3.3-V
LVCMOS
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
3.0-V LVTTL
GCLK ^tsu
PLL _th
3.0-V
LVCMOS
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
2.5 V
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
-0.986
1.119
-1.278
1.556
-0.986
1.119
-1.278
1.556
-0.997
1.130
-1.289
1.567
-0.997
1.130
-1.289
1.567
-0.992
1.125
-1.284
1.562
-0.964
1.093
-1.221
1.499
-0.964
1.093
-1.221
1.499
-0.975
1.104
-1.232
1.510
-0.975
1.104
-1.232
1.510
-0.970
1.099
-1.227
1.505
-1.402 -1.558 -1.797 -1.778 -2.106 -1.558 -1.797 -1.778 -2.106 ns
1.584 1.767 2.027 1.996 2.327 1.767 2.027 1.996 2.327 ns
-1.771 -1.984 -2.197 -2.123 -2.542 -1.984 -2.197 -2.123 -2.542 ns
2.175 2.439 2.697 2.598 3.034 2.439 2.697 2.598 3.034 ns
-1.402 -1.558 -1.797 -1.778 -2.106 -1.558 -1.797 -1.778 -2.106 ns
1.584 1.767 2.027 1.996 2.327 1.767 2.027 1.996 2.327 ns
-1.771 -1.984 -2.197 -2.123 -2.542 -1.984 -2.197 -2.123 -2.542 ns
2.175 2.439 2.697 2.598 3.034 2.439 2.697 2.598 3.034 ns
-1.401 -1.560 -1.796 -1.777 -2.105 -1.560 -1.796 -1.777 -2.105 ns
1.583 1.769 2.026 1.995 2.326 1.769 2.026 1.995 2.326 ns
-1.770 -1.986 -2.196 -2.122 -2.541 -1.986 -2.196 -2.122 -2.541 ns
2.174 2.441 2.696 2.597 3.033 2.441 2.696 2.597 3.033 ns
-1.401 -1.560 -1.796 -1.777 -2.105 -1.560 -1.796 -1.777 -2.105 ns
1.583 1.769 2.026 1.995 2.326 1.769 2.026 1.995 2.326 ns
-1.770 -1.986 -2.196 -2.122 -2.541 -1.986 -2.196 -2.122 -2.541 ns
2.174 2.441 2.696 2.597 3.033 2.441 2.696 2.597 3.033 ns
-1.410 -1.572 -1.815 -1.796 -2.124 -1.572 -1.815 -1.796 -2.124 ns
1.592 1.781 2.045 2.014 2.345 1.781 2.045 2.014 2.345 ns
-1.779 -1.998 -2.215 -2.141 -2.560 -1.998 -2.215 -2.141 -2.560 ns
2.183 2.453 2.715 2.616 3.052 2.453 2.715 2.616 3.052 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2