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EP3SE80F780I4N Datasheet, PDF (36/341 Pages) Altera Corporation – Chapter Revision Dates | |||
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1â26
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
.
Table 1â28. Sampling Window (SW)âRead Side (Note 1)
C2
C3, I3
C4, I4
C4L, I4L
C4L, I4L
Memory Type
I/O
Standard
Width
VCCL = 1.1 V
SW (ps)
VCCL = 1.1 V
SW (ps)
VCCL = 1.1 V
SW (ps)
VCCL = 1.1 V
SW (ps)
VCCL = 0.9 V
SW (ps)
DDR3 SDRAM (with 8 or
10 tap phase offset,
300 MHzâ400 MHz)
DDR3 SDRAM (with
Deskew circuitry,
401 MHzâ533 MHz)
1.5-V
SSTL
1.5-V
SSTL
Ã4, Ã8
Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold
172 296 234 296 257 311 257 311 257 311
Ã4, Ã8 300 213 â â â â â â â â
DDR3 SDRAM
(Non-leveling interface)
DDR2 SDRAM Differential
DQS
DDR2 SDRAM
Single-ended DQS
DDR SDRAM
Single-ended DQS
1.5-V
SSTL
1.8-V
SSTL
1.8-V
SSTL
2.5-V
SSTL
Ã4, Ã8 172 296 234 296 257 311 257 311 257 311
Ã4, Ã8 181 306 234 326 257 326 257 326 257 326
Ã4, Ã8 231 256 284 276 307 276 307 276 307 276
Ã4, Ã8 231 256 284 261 307 261 307 261 307 261
QDRII/II+ SRAM
QDRII/II+ SRAM
Emulation (2)
1.5-V
HSTL
1.5-V
HSTL
Ã9, Ã18, 261 286 314 291 337 291 337 291 337 291
Ã36
Ã36
261 328 314 337 337 350 337 350 337 350
QDRII/II+ SRAM
QDRII/II+ SRAM
Emulation (2)
RLDRAM II
1.8-V
HSTL
1.8-V
HSTL
1.5-V
HSTL
Ã9, Ã18, 261 286 314 291 337 291 337 291 337 291
Ã36
Ã36
261 328 314 337 337 350 337 350 337 350
Ã9, Ã18 211 336 264 356 287 356 287 356 287 356
RLDRAM II
1.8-V
HSTL
Ã9, Ã18 211 336 264 356 287 356 287 356 287 356
Notes to Table 1â28:
(1) The values apply to Column I/Os, Row I/Os and Hybrid mode interface. Column I/Os refer to top and bottom I/Os. Hybrid mode refers to DQ/DQS groups
wrapping over Column I/Os and Row I/Os of the device.
(2) For implementation, refer to the âSupporting Ã36 QDRII+/QDRII SRAM Interfaces in the F780 and F1152-Pin Packagesâ section in the External Memory
Interfaces in Stratix III Devices chapter.
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation
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