EP3SE80F780I4N Datasheet, PDF (190/341 Pages) Altera Corporation – Chapter Revision Dates

1–180
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–93 lists the EP3SL340 column pins output timing parameters for single-ended
I/O standards.
Table 1–93. EP3SL340 Column Pins Output Timing Parameters (Part 1 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co 3.705
4mA
GCLK
PLL ^tco
4.269
3.705
4.269
5.372 5.559 6.083 5.935 6.364 5.559 6.083 5.935 6.364 ns
6.214 6.409 6.992 6.812 7.355 6.409 6.992 6.812 7.355 ns
3.3-V
LVTTL
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.638
4.202
3.552
4.116
3.638
4.202
3.552
4.116
5.263 5.448 5.970 5.822 6.251 5.448 5.970 5.822 6.251 ns
6.105 6.298 6.879 6.699 7.242 6.298 6.879 6.699 7.242 ns
5.160 5.350 5.878 5.730 6.159 5.350 5.878 5.730 6.159 ns
6.001 6.200 6.789 6.609 7.152 6.200 6.789 6.609 7.152 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.545
4.110
3.545
4.110
5.143 5.322 5.837 5.689 6.118 5.322 5.837 5.689 6.118 ns
5.985 6.172 6.747 6.567 7.110 6.172 6.747 6.567 7.110 ns
GCLK t_co 3.711
4mA
GCLK
PLL ^tco
4.275
3.711
4.275
5.377 5.564 6.090 5.942 6.371 5.564 6.090 5.942 6.371 ns
6.218 6.414 7.000 6.820 7.363 6.414 7.000 6.820 7.363 ns
3.3-V
LVCMOS
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.556
4.120
3.563
4.127
3.556
4.120
3.563
4.127
5.170 5.367 5.889 5.741 6.170 5.367 5.889 5.741 6.170 ns
6.012 6.217 6.799 6.619 7.162 6.217 6.799 6.619 7.162 ns
5.164 5.346 5.863 5.715 6.144 5.346 5.863 5.715 6.144 ns
6.006 6.196 6.775 6.595 7.138 6.196 6.775 6.595 7.138 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.547
4.111
3.547
4.111
5.141 5.320 5.834 5.686 6.115 5.320 5.834 5.686 6.115 ns
5.983 6.171 6.746 6.566 7.109 6.171 6.746 6.566 7.109 ns
GCLK t_co 3.669
4mA
GCLK
PLL ^tco
4.232
3.669
4.232
5.339 5.528 6.050 5.902 6.331 5.528 6.050 5.902 6.331 ns
6.181 6.377 6.983 6.803 7.346 6.377 6.983 6.803 7.346 ns
3.0-V
LVTTL
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.558
4.125
3.522
4.087
3.558
4.125
3.522
4.087
5.209 5.394 5.912 5.765 6.193 5.394 5.912 5.765 6.193 ns
6.053 6.246 6.867 6.688 7.229 6.246 6.867 6.688 7.229 ns
5.146 5.325 5.838 5.691 6.119 5.325 5.838 5.691 6.119 ns
5.987 6.174 6.803 6.624 7.165 6.174 6.803 6.624 7.165 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.504
4.068
3.504
4.068
5.117 5.297 5.810 5.662 6.091 5.297 5.810 5.662 6.091 ns
5.959 6.147 6.780 6.601 7.142 6.147 6.780 6.601 7.142 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation