EP3SE80F780I4N Datasheet, PDF (163/341 Pages) Altera Corporation – Chapter Revision Dates

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–153
Table 1–83. EP3SL200 Column Pins Output Timing Parameters (Part 2 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
4mA
GCLK t_co
GCLK
PLL ^tco
3.555
3.954
3.555
3.954
5.173 5.360 5.861 5.719 6.123 5.360 5.861 5.719 6.123 ns
5.808 6.000 6.566 6.395 6.880 6.000 6.566 6.395 6.880 ns
3.0-V
LVCMOS
8mA
GCLK t_co
GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.476
3.875
3.471
3.870
3.476
3.875
3.471
3.870
5.049 5.231 5.726 5.584 5.988 5.231 5.726 5.584 5.988 ns
5.684 5.871 6.431 6.260 6.745 5.871 6.431 6.260 6.745 ns
5.042 5.224 5.718 5.575 5.980 5.224 5.718 5.575 5.980 ns
5.677 5.864 6.422 6.250 6.737 5.864 6.422 6.250 6.737 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.462
3.861
3.462
3.861
5.028 5.209 5.703 5.560 5.965 5.209 5.703 5.560 5.965 ns
5.663 5.849 6.407 6.235 6.722 5.849 6.407 6.235 6.722 ns
4mA
GCLK t_co
GCLK
PLL ^tco
3.677
4.076
3.677
4.076
5.380 5.587 6.108 5.966 6.370 5.587 6.108 5.966 6.370 ns
6.015 6.227 6.813 6.642 7.127 6.227 6.813 6.642 7.127 ns
GCLK t_co 3.577
3.577 5.261 5.461 5.976 5.834 6.238 5.461 5.976 5.834 6.238 ns
8mA _GCLK
PLL ^tco
3.976
3.976 5.896 6.101 6.681 6.510 6.995 6.101 6.681 6.510 6.995 ns
2.5 V
GCLK t_co 3.533
3.533 5.174 5.370 5.881 5.738 6.143 5.370 5.881 5.738 6.143 ns
12mA _GCLK
PLL ^tco
3.932
3.932 5.809 6.010 6.585 6.413 6.900 6.010 6.585 6.413 6.900 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.495
3.894
3.495
3.894
5.135 5.328 5.838 5.695 6.100 5.328 5.838 5.695 6.100 ns
5.770 5.968 6.542 6.370 6.857 5.968 6.542 6.370 6.857 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2