EP3SE80F780I4N Datasheet, PDF (167/341 Pages) Altera Corporation – Chapter Revision Dates

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–157
Table 1–83. EP3SL200 Column Pins Output Timing Parameters (Part 6 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
4mA
GCLK t_co
GCLK
PLL ^tco
3.516
3.915
3.516
3.915
5.153 5.348 5.856 5.713 6.118 5.348 5.856 5.713 6.118 ns
5.788 5.988 6.560 6.388 6.875 5.988 6.560 6.388 6.875 ns
6mA
GCLK t_co
GCLK
PLL ^tco
3.509
3.908
3.509
3.908
5.151 5.346 5.855 5.712 6.117 5.346 5.855 5.712 6.117 ns
5.786 5.986 6.559 6.387 6.874 5.986 6.559 6.387 6.874 ns
1.8-V
HSTL
CLASS I
8mA
GCLK t_co
GCLK
PLL ^tco
3.501
3.900
3.501
3.900
5.143 5.339 5.848 5.705 6.110 5.339 5.848 5.705 6.110 ns
5.778 5.979 6.552 6.380 6.867 5.979 6.552 6.380 6.867 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.504
3.903
3.504
3.903
5.146 5.342 5.852 5.709 6.114 5.342 5.852 5.709 6.114 ns
5.781 5.982 6.556 6.384 6.871 5.982 6.556 6.384 6.871 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.501
3.900
3.501
3.900
5.149 5.346 5.856 5.713 6.118 5.346 5.856 5.713 6.118 ns
5.784 5.986 6.560 6.388 6.875 5.986 6.560 6.388 6.875 ns
1.8-V
HSTL
CLASS II
GCLK t_co
16mA _GCLK
PLL ^tco
3.509
3.908
3.509
3.908
5.148 5.343 5.852 5.709 6.114 5.343 5.852 5.709 6.114 ns
5.783 5.983 6.556 6.384 6.871 5.983 6.556 6.384 6.871 ns
4mA
GCLK t_co
GCLK
PLL ^tco
3.521
3.920
3.521
3.920
5.161 5.358 5.867 5.724 6.129 5.358 5.867 5.724 6.129 ns
5.796 5.998 6.571 6.399 6.886 5.998 6.571 6.399 6.886 ns
6mA
GCLK t_co
GCLK
PLL ^tco
3.517
3.916
3.517
3.916
5.162 5.359 5.870 5.727 6.132 5.359 5.870 5.727 6.132 ns
5.797 5.999 6.574 6.402 6.889 5.999 6.574 6.402 6.889 ns
1.5-V
HSTL
CLASS I
8mA
GCLK t_co
GCLK
PLL ^tco
3.513
3.912
3.513
3.912
5.158 5.355 5.865 5.722 6.127 5.355 5.865 5.722 6.127 ns
5.793 5.995 6.569 6.397 6.884 5.995 6.569 6.397 6.884 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.506
3.905
3.506
3.905
5.151 5.348 5.858 5.715 6.120 5.348 5.858 5.715 6.120 ns
5.786 5.988 6.562 6.390 6.877 5.988 6.562 6.390 6.877 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.507
3.906
3.507
3.906
5.158 5.356 5.868 5.725 6.130 5.356 5.868 5.725 6.130 ns
5.793 5.996 6.572 6.400 6.887 5.996 6.572 6.400 6.887 ns
1.5-V
HSTL
CLASS II
GCLK t_co
16mA _GCLK
PLL ^tco
3.505
3.904
3.505
3.904
5.139 5.334 5.842 5.699 6.104 5.334 5.842 5.699 6.104 ns
5.774 5.974 6.546 6.374 6.861 5.974 6.546 6.374 6.861 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2