EP3SE80F780I4N Datasheet, PDF (137/341 Pages) Altera Corporation – Chapter Revision Dates

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–127
Table 1–73. EP3SL150 Column Pins Output Timing Parameters (Part 4 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co 3.559
2mA
GCLK
PLL ^tco
4.069
3.576
3.978
5.096 5.515 6.079 5.927 6.262 5.515 6.079 5.927 6.262 ns
5.683 6.384 6.795 6.615 6.997 6.384 6.795 6.615 6.997 ns
GCLK t_co 3.347
4mA
GCLK
PLL ^tco
3.786
3.364
3.766
4.777 5.158 5.687 5.535 5.870 5.158 5.687 5.535 5.870 ns
5.364 5.871 6.403 6.223 6.605 5.871 6.403 6.223 6.605 ns
GCLK t_co 3.322
3.339 4.710 5.098 5.620 5.468 5.803 5.098 5.620 5.468 5.803 ns
6mA
GCLK
PLL ^tco
3.745
3.741 5.297 5.763 6.336 6.156 6.538 5.763 6.336 6.156 6.538 ns
1.5 V
GCLK t_co 3.311
3.328 4.693 5.073 5.600 5.448 5.783 5.073 5.600 5.448 5.783 ns
8mA
GCLK
PLL ^tco
3.734
3.730 5.280 5.742 6.316 6.136 6.518 5.742 6.316 6.136 6.518 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.256
3.679
3.273
3.675
4.655 5.023 5.530 5.378 5.713 5.023 5.530 5.378 5.713 ns
5.242 5.688 6.246 6.066 6.448 5.688 6.246 6.066 6.448 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.251
3.674
3.268
3.670
4.638 5.011 5.519 5.367 5.702 5.011 5.519 5.367 5.702 ns
5.225 5.676 6.235 6.055 6.437 5.676 6.235 6.055 6.437 ns
GCLK t_co 3.475
2mA
GCLK
PLL ^tco
3.959
3.492
3.894
5.022 5.450 6.023 5.871 6.206 5.450 6.023 5.871 6.206 ns
5.609 6.283 6.739 6.559 6.941 6.283 6.739 6.559 6.941 ns
GCLK t_co 3.352
3.369 4.796 5.189 5.737 5.585 5.920 5.189 5.737 5.585 5.920 ns
4mA
GCLK
PLL ^tco
3.786
3.771 5.383 5.902 6.453 6.273 6.655 5.902 6.453 6.273 6.655 ns
1.2 V
GCLK t_co 3.314
3.331 4.704 5.099 5.624 5.472 5.807 5.099 5.624 5.472 5.807 ns
6mA
GCLK
PLL ^tco
3.737
3.733 5.291 5.764 6.340 6.160 6.542 5.764 6.340 6.160 6.542 ns
GCLK t_co 3.267
8mA
GCLK
PLL ^tco
3.690
3.284
3.686
4.676 5.050 5.568 5.416 5.751 5.050 5.568 5.416 5.751 ns
5.263 5.715 6.284 6.104 6.486 5.715 6.284 6.104 6.486 ns
GCLK t_co 3.267
8mA
GCLK
PLL ^tco
3.690
3.284
3.686
4.633 4.998 5.499 5.347 5.682 4.998 5.499 5.347 5.682 ns
5.220 5.663 6.215 6.035 6.417 5.663 6.215 6.035 6.417 ns
SSTL-2
CLASS I
GCLK t_co
10mA _GCLK
PLL ^tco
3.264
3.687
3.281
3.683
4.630 4.994 5.495 5.343 5.678 4.994 5.495 5.343 5.678 ns
5.217 5.659 6.211 6.031 6.413 5.659 6.211 6.031 6.413 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.262
3.685
3.279
3.681
4.630 4.995 5.496 5.344 5.679 4.995 5.496 5.344 5.679 ns
5.217 5.660 6.212 6.032 6.414 5.660 6.212 6.032 6.414 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2