EP3SE80F780I4N Datasheet, PDF (55/341 Pages) Altera Corporation – Chapter Revision Dates

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–45
Table 1–43. EP3SL50 Column Pins output Timing Parameters (Part 2 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
3.0-V
LVCMOS
2.5 V
GCLK t_co
4mA _GCLK
PLL ^tco
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
GCLK t_co
16mA _GCLK
PLL ^tco
GCLK t_co
4mA _GCLK
PLL ^tco
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
GCLK t_co
16mA _GCLK
PLL ^tco
3.046
3.402
2.967
3.323
2.962
3.318
2.953
3.309
3.168
3.524
3.068
3.424
3.024
3.380
2.986
3.342
3.034
3.402
2.955
3.323
2.950
3.318
2.941
3.309
3.156
3.524
3.056
3.424
3.012
3.380
2.974
3.342
4.253 4.610 5.075 4.958 5.157 4.610 5.075 4.958 5.157 ns
4.776 5.172 5.685 5.543 5.808 5.172 5.685 5.543 5.808 ns
4.130 4.481 4.940 4.823 5.022 4.481 4.940 4.823 5.022 ns
4.652 5.043 5.550 5.408 5.673 5.043 5.550 5.408 5.673 ns
4.122 4.474 4.931 4.813 5.015 4.474 4.931 4.813 5.015 ns
4.645 5.036 5.541 5.398 5.665 5.036 5.541 5.398 5.665 ns
4.108 4.459 4.916 4.798 5.000 4.459 4.916 4.798 5.000 ns
4.631 5.021 5.526 5.383 5.650 5.021 5.526 5.383 5.650 ns
4.460 4.837 5.322 5.205 5.405 4.837 5.322 5.205 5.405 ns
4.983 5.399 5.932 5.790 6.055 5.399 5.932 5.790 6.055 ns
4.341 4.711 5.190 5.073 5.272 4.711 5.190 5.073 5.272 ns
4.864 5.273 5.800 5.658 5.923 5.273 5.800 5.658 5.923 ns
4.254 4.620 5.094 4.976 5.178 4.620 5.094 4.976 5.178 ns
4.777 5.182 5.704 5.561 5.828 5.182 5.704 5.561 5.828 ns
4.215 4.578 5.051 4.933 5.135 4.578 5.051 4.933 5.135 ns
4.738 5.140 5.661 5.518 5.785 5.140 5.661 5.518 5.785 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2