EP3SE80F780I4N Datasheet, PDF (193/341 Pages) Altera Corporation – Chapter Revision Dates

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–183
Table 1–93. EP3SL340 Column Pins Output Timing Parameters (Part 4 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co 3.758
2mA
GCLK
PLL ^tco
4.322
3.758
4.322
5.626 5.882 6.481 6.333 6.762 5.882 6.481 6.333 6.762 ns
6.468 6.731 7.392 7.212 7.755 6.731 7.392 7.212 7.755 ns
GCLK t_co 3.635
3.635 5.401 5.621 6.195 6.047 6.476 5.621 6.195 6.047 6.476 ns
4mA
GCLK
PLL ^tco
4.200
4.200 6.243 6.471 7.107 6.927 7.470 6.471 7.107 6.927 7.470 ns
1.2 V
GCLK t_co 3.597
3.597 5.308 5.531 6.082 5.934 6.363 5.531 6.082 5.934 6.363 ns
6mA
GCLK
PLL ^tco
4.162
4.162 6.150 6.381 6.993 6.813 7.356 6.381 6.993 6.813 7.356 ns
GCLK t_co 3.550
8mA
GCLK
PLL ^tco
4.113
3.550
4.113
5.280 5.482 6.026 5.878 6.307 5.482 6.026 5.878 6.307 ns
6.121 6.331 6.946 6.766 7.309 6.331 6.946 6.766 7.309 ns
GCLK t_co 3.550
8mA
GCLK
PLL ^tco
4.114
3.550
4.114
5.237 5.430 5.957 5.809 6.238 5.430 5.957 5.809 6.238 ns
6.078 6.278 6.903 6.723 7.266 6.278 6.903 6.723 7.266 ns
SSTL-2
CLASS I
GCLK t_co
10mA _GCLK
PLL ^tco
3.547
4.111
3.547
4.111
5.234 5.426 5.953 5.805 6.234 5.426 5.953 5.805 6.234 ns
6.075 6.274 6.899 6.720 7.261 6.274 6.899 6.720 7.261 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.545
4.110
3.545
4.110
5.234 5.427 5.954 5.806 6.235 5.427 5.954 5.806 6.235 ns
6.075 6.275 6.899 6.719 7.262 6.275 6.899 6.719 7.262 ns
SSTL-2
CLASS II
GCLK t_co
16mA _GCLK
PLL ^tco
3.536
4.101
3.536
4.101
5.220 5.412 5.939 5.791 6.220 5.412 5.939 5.791 6.220 ns
6.062 6.261 6.883 6.703 7.246 6.261 6.883 6.703 7.246 ns
GCLK t_co 3.557
4mA
GCLK
PLL ^tco
4.121
3.557
4.121
5.249 5.444 5.973 5.825 6.254 5.444 5.973 5.825 6.254 ns
6.090 6.292 6.923 6.744 7.285 6.292 6.923 6.744 7.285 ns
GCLK t_co 3.553
6mA
GCLK
PLL ^tco
4.117
3.553
4.117
5.247 5.442 5.971 5.823 6.252 5.442 5.971 5.823 6.252 ns
6.088 6.290 6.920 6.740 7.283 6.290 6.920 6.740 7.283 ns
GCLK t_co 3.542
SSTL-18
CLASS I
8mA
GCLK
PLL ^tco
4.107
3.542
4.107
5.237 5.432 5.962 5.814 6.243 5.432 5.962 5.814 6.243 ns
6.079 6.281 6.919 6.740 7.281 6.281 6.919 6.740 7.281 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.531
4.095
3.531
4.095
5.225 5.419 5.949 5.801 6.230 5.419 5.949 5.801 6.230 ns
6.066 6.268 6.894 6.715 7.256 6.268 6.894 6.715 7.256 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.531
4.095
3.531
4.095
5.224 5.419 5.949 5.801 6.230 5.419 5.949 5.801 6.230 ns
6.066 6.268 6.892 6.712 7.255 6.268 6.892 6.712 7.255 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2