EP3SE80F780I4N Datasheet, PDF (236/341 Pages) Altera Corporation – Chapter Revision Dates

1–226
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–108. EP3SE50 Row Pins Output Timing Parameters (Part 2 of 3)
I/O Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
4mA _GCLK
PLL ^tco
3.123
3.108
3.359
3.344
4.763 5.180 5.707 5.564 5.767 5.316 5.847 5.702 5.838 ns
4.749 5.165 5.692 5.549 5.752 5.301 5.832 5.687 5.823 ns
DIFFERENTIAL
1.5-V
6mA
HSTL CLASS I
GCLK t_co
GCLK
PLL ^tco
3.097
3.077
3.333
3.313
4.744 5.162 5.689 5.546 5.749 5.298 5.830 5.685 5.821 ns
4.721 5.138 5.666 5.523 5.726 5.275 5.806 5.661 5.797 ns
GCLK t_co
8mA _GCLK
PLL ^tco
3.074
3.079
3.309
3.313
4.717 5.135 5.662 5.519 5.722 5.271 5.803 5.658 5.794 ns
4.708 5.123 5.648 5.505 5.708 5.258 5.787 5.642 5.778 ns
GCLK t_co
4mA _GCLK
PLL ^tco
3.072
3.100
3.306
3.335
4.707 5.124 5.651 5.508 5.711 5.261 5.792 5.647 5.783 ns
4.735 5.151 5.677 5.534 5.737 5.287 5.817 5.672 5.808 ns
GCLK t_co
6mA _GCLK
PLL ^tco
3.082
3.068
3.318
3.302
4.720 5.136 5.662 5.519 5.722 5.272 5.802 5.657 5.793 ns
4.697 5.112 5.637 5.494 5.697 5.248 5.777 5.632 5.768 ns
DIFFERENTIAL
1.8-V
8mA
HSTL CLASS I
GCLK t_co
GCLK
PLL ^tco
2.674
3.068
2.849
3.295
3.990 4.359 4.834 4.699 4.910 4.467 4.945 4.809 4.961 ns
4.657 5.068 5.588 5.445 5.648 5.200 5.724 5.579 5.715 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.050
2.674
3.285
2.849
4.695 5.114 5.642 5.499 5.702 5.251 5.785 5.640 5.776 ns
3.990 4.359 4.834 4.699 4.910 4.467 4.945 4.809 4.961 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.068
3.050
3.295
3.285
4.657 5.068 5.588 5.445 5.648 5.200 5.724 5.579 5.715 ns
4.695 5.114 5.642 5.499 5.702 5.251 5.785 5.640 5.776 ns
DIFFERENTIAL
GCLK t_co
1.8-V
16mA _GCLK
HSTL CLASS II
PLL ^tco
2.674
3.068
2.849
3.295
3.990 4.359 4.834 4.699 4.910 4.467 4.945 4.809 4.961 ns
4.657 5.068 5.588 5.445 5.648 5.200 5.724 5.579 5.715 ns
GCLK t_co
4mA _GCLK
PLL ^tco
3.050
3.104
3.285
3.338
4.695 5.114 5.642 5.499 5.702 5.251 5.785 5.640 5.776 ns
4.741 5.158 5.685 5.542 5.745 5.294 5.824 5.679 5.815 ns
DIFFERENTIAL
1.5-V
6mA
SSTL CLASS I
GCLK t_co
GCLK
PLL ^tco
3.090
3.086
3.324
3.320
4.728 5.145 5.672 5.529 5.732 5.280 5.811 5.666 5.802 ns
4.726 5.145 5.673 5.530 5.733 5.280 5.813 5.668 5.804 ns
GCLK t_co
8mA _GCLK
PLL ^tco
3.102
3.091
3.335
3.325
4.727 5.142 5.667 5.524 5.727 5.277 5.806 5.661 5.797 ns
4.723 5.138 5.664 5.521 5.724 5.274 5.803 5.658 5.794 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation