EP3SE80F780I4N Datasheet, PDF (72/341 Pages) Altera Corporation – Chapter Revision Dates

1–62
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–47. EP3SL50 Column Pins Output Timing Parameters (Part 4 of 4)
I/O Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
8mA
GCLK
PLL
t_co
DIFFERENTIAL
2.5-V SSTL
GCLK t_co
CLASS I
10mA _GCLK
PLL
t_co
GCLK t_co
12mA _GCLK
PLL
t_co
DIFFERENTIAL
GCLK t_co
2.5-V SSTL
CLASS II
16mA _GCLK
PLL
t_co
3.034
3.032
3.036
3.036
3.052
3.052
3.042
3.035
3.258
3.256
3.258
3.259
3.276
3.276
3.266
3.258
4.627 5.034 5.551 5.411 5.629 5.162 5.680 5.542 5.699 ns
4.625 5.032 5.549 5.409 5.627 5.160 5.677 5.539 5.696 ns
4.617 5.022 5.537 5.397 5.615 5.149 5.664 5.526 5.683 ns
4.625 5.032 5.549 5.409 5.627 5.160 5.677 5.539 5.696 ns
4.641 5.047 5.563 5.423 5.641 5.175 5.690 5.552 5.709 ns
4.641 5.047 5.563 5.423 5.641 5.175 5.690 5.552 5.709 ns
4.631 5.037 5.553 5.413 5.631 5.165 5.681 5.543 5.700 ns
4.617 5.022 5.537 5.397 5.615 5.149 5.664 5.526 5.683 ns
Table 1–48 lists the EP3SL50 row pins output timing parameters for differential I/O
standards.
Table 1–48. EP3SL50 Row Pins Output Timing Parameters (Part 1 of 4)
I/O Standard
LVDS
LVDS_E_1R
LVDS_E_3R
MINI-LVDS
MINI-
LVDS_E_1R
MINI-
LVDS_E_3R
RSDS
Clock
Fast Model
Industrial Commercial
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co 2.668
—
GCLK
PLL ^tco
3.062
2.842
3.288
3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.795 4.940 ns
4.646 5.055 5.575 5.431 5.630 5.186 5.709 5.565 5.694 ns
GCLK t_co 3.044
—
GCLK
PLL ^tco
2.668
3.278
2.842
4.684 5.101 5.629 5.485 5.684 5.237 5.770 5.626 5.755 ns
3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.795 4.940 ns
GCLK t_co 3.062
—
GCLK
PLL ^tco
3.044
3.288
3.278
4.646 5.055 5.575 5.431 5.630 5.186 5.709 5.565 5.694 ns
4.684 5.101 5.629 5.485 5.684 5.237 5.770 5.626 5.755 ns
GCLK t_co 2.668
—
GCLK
PLL ^tco
3.062
2.842
3.288
3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.795 4.940 ns
4.646 5.055 5.575 5.431 5.630 5.186 5.709 5.565 5.694 ns
GCLK t_co 3.044
—
GCLK
PLL ^tco
3.098
3.278
3.331
4.684 5.101 5.629 5.485 5.684 5.237 5.770 5.626 5.755 ns
4.730 5.145 5.672 5.528 5.727 5.280 5.809 5.665 5.794 ns
GCLK t_co 3.084
—
GCLK
PLL ^tco
3.080
3.317
3.313
4.717 5.132 5.659 5.515 5.714 5.266 5.796 5.652 5.781 ns
4.715 5.132 5.660 5.516 5.715 5.266 5.798 5.654 5.783 ns
GCLK t_co 3.096
—
GCLK
PLL ^tco
3.085
3.328
3.318
4.716 5.129 5.654 5.510 5.709 5.263 5.791 5.647 5.776 ns
4.712 5.125 5.651 5.507 5.706 5.260 5.788 5.644 5.773 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation