EP3SE80F780I4N Datasheet, PDF (126/341 Pages) Altera Corporation – Chapter Revision Dates

1–116
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–68 lists the EP3SL110 row pins output timing parameters for differential I/O
standards.
Table 1–68. EP3SL110 Row Pins Output Timing Parameters (Part 1 of 3)
I/O Standard
Clock
Fast Model
Industrial Commercial
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
LVDS
GCLK t_co 2.711
—
GCLK
PLL ^tco
0.934
2.894
1.059
4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035 ns
1.248 1.300 1.459 1.480 1.491 1.379 1.542 1.561 1.459 ns
LVDS_E_1R —
GCLK t_co
GCLK
PLL ^tco
3.106
1.326
3.342
1.503
4.709 5.107 5.611 5.475 5.730 5.229 5.736 5.599 5.802 ns
1.919 2.016 2.222 2.235 2.238 2.120 2.330 2.340 2.222 ns
LVDS_E_3R —
GCLK t_co
GCLK
PLL ^tco
3.088
1.308
3.332
1.493
4.747 5.153 5.665 5.529 5.784 5.280 5.797 5.660 5.863 ns
1.957 2.062 2.276 2.289 2.292 2.171 2.391 2.401 2.283 ns
GCLK t_co 2.711
MINI-LVDS
—
GCLK
PLL ^tco
0.934
2.894
1.059
4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035 ns
1.248 1.300 1.459 1.480 1.491 1.379 1.542 1.561 1.459 ns
MINI-
LVDS_E_1R
—
GCLK t_co
GCLK
PLL ^tco
3.106
1.326
3.342
1.503
4.709 5.107 5.611 5.475 5.730 5.229 5.736 5.599 5.802 ns
1.919 2.016 2.222 2.235 2.238 2.120 2.330 2.340 2.222 ns
MINI-
LVDS_E_3R
—
GCLK t_co
GCLK
PLL ^tco
3.088
1.308
3.332
1.493
4.747 5.153 5.665 5.529 5.784 5.280 5.797 5.660 5.863 ns
1.957 2.062 2.276 2.289 2.292 2.171 2.391 2.401 2.283 ns
RSDS
GCLK t_co 2.711
—
GCLK
PLL ^tco
0.934
2.894
1.059
4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035 ns
1.248 1.300 1.459 1.480 1.491 1.379 1.542 1.561 1.459 ns
RSDS_E_1R —
GCLK t_co
GCLK
PLL ^tco
3.106
1.326
3.342
1.503
4.709 5.107 5.611 5.475 5.730 5.229 5.736 5.599 5.802 ns
1.919 2.016 2.222 2.235 2.238 2.120 2.330 2.340 2.222 ns
RSDS_E_3R —
GCLK t_co
GCLK
PLL ^tco
3.088
1.308
3.332
1.493
4.747 5.153 5.665 5.529 5.784 5.280 5.797 5.660 5.863 ns
1.957 2.062 2.276 2.289 2.292 2.171 2.391 2.401 2.283 ns
DIFFERENTIAL
1.2-V
4mA
HSTL CLASS I
GCLK t_co
GCLK
PLL ^tco
3.132
1.352
3.375
1.536
4.783 5.187 5.698 5.562 5.817 5.313 5.826 5.689 5.892 ns
1.993 2.096 2.309 2.322 2.325 2.204 2.420 2.430 2.312 ns
DIFFERENTIAL
1.2-V
6mA
HSTL CLASS I
GCLK t_co
GCLK
PLL ^tco
3.118
1.338
3.361
1.522
4.770 5.174 5.685 5.549 5.804 5.299 5.813 5.676 5.879 ns
1.980 2.083 2.296 2.309 2.312 2.190 2.407 2.417 2.299 ns
DIFFERENTIAL
1.2-V
8mA
HSTL CLASS I
GCLK t_co
GCLK
PLL ^tco
3.114
1.334
3.357
1.518
4.768 5.174 5.686 5.550 5.805 5.299 5.815 5.678 5.881 ns
1.978 2.083 2.297 2.310 2.313 2.190 2.409 2.419 2.301 ns
DIFFERENTIAL
1.5-V
4mA
HSTL CLASS I
GCLK t_co
GCLK
PLL ^tco
3.130
1.350
3.372
1.533
4.769 5.171 5.680 5.544 5.799 5.296 5.808 5.671 5.874 ns
1.979 2.080 2.291 2.304 2.307 2.187 2.402 2.412 2.294 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation