EP3SE80F780I4N Datasheet, PDF (39/341 Pages) Altera Corporation – Chapter Revision Dates

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
1–29
Table 1–31 lists the average DQS phase offset delay per setting for Stratix III devices.
Table 1–31. Average DQS Phase Offset Delay per Setting for Stratix III Devices (Note 1), (2), (3)
Speed Grade
Min
Typ
Max
Unit
C2
7
10
13
ps
C3, I3
7
11
15
ps
C4, I4
7
11.5
16
ps
C4L, I4L
7
11.5
16
ps
Notes to Table 1–31:
(1) The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes
4 to 6.
(2) The typical value equals the average of the minimum and maximum values.
(3) The delay settings are linear with a cumulative delay variation of ± 20 ps for all speed grades. For example, when
using a C2 speed grade and applying 10° phase offset settings to a 90° phase shift at 400 MHz, the expected
minimum cumulative delay is [625 ps + (10*7 ps) - 20 ps] = 675 ps.
Table 1–32 lists the DQS phase shift error specification for DLL-delayed clock
(t_{DQS_PSERR}) for Stratix III devices.
Table 1–32. DQS Phase Shift Error Specification for DLL-Delayed Clock (t_{DQS_PSERR}) for Stratix III Devices (Note 1)
Number of DQS Delay
Buffer
C2
C3, I3
C4, C4L, I4, I4L
Unit
1
±13
±14
±15
ps
2
±26
±28
±30
ps
3
±39
±42
±45
ps
4
±52
±56
±60
ps
Note to Table 1–32:
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay buffers in a C2 speed grade is
± 39 ps.
Table 1–33 lists the memory output jitter specification for Stratix III devices.
Table 1–33. Memory Output Clock Jitter Specification for Stratix III Devices (Note 1), (2)
Parameter
C2
C3, I3
C4, I4
C4L, I4L
Clock
Network
Symbol
V_CCL = 1.1V
V_CCL = 1.1V
V_CCL = 1.1V
V_CCL = 1.1V
V_CCL = 0.9V
Unit
Min Max Min Max Min Max Min Max Min Max
Clock period jitter
Regional tJIT(per) –75 75 –85 85 –100 100 –100 100 –120 120 ps
Cycle-to-cycle period jitter Regional tJIT(cc) –150 150 –170 170 –190 190 –190 190 –230 230 ps
Duty cycle jitter
Regional tJIT(duty) –80 80 –90 90 –100 100 –100 100 –140 140 ps
Clock period jitter
Global tJIT(per) –113 113 –128 128 –150 150 –150 150 –180 180 ps
Cycle-to-cycle period jitter Global tJIT(cc) –225 225 –255 255 –285 285 –285 285 –340 340 ps
Duty cycle jitter
Global tJIT(duty) –120 120 –135 135 –150 150 –150 150 –180 180 ps
Notes to Table 1–33:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 standard.
(2) The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL output routed
on a regional or global clock network as specified. Altera recommends using the regional clock networks whenever possible.
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2