EP3SE80F780I4N Datasheet, PDF (111/341 Pages) Altera Corporation – Chapter Revision Dates

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–101
Table 1–63. EP3SL110 Column Pins Output Timing Parameters (Part 4 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co 3.576
2mA
GCLK
PLL ^tco
3.966
3.576
3.966
5.096 5.533 6.092 5.961 6.255 5.533 6.092 5.961 6.255 ns
5.672 6.165 6.780 6.622 7.004 6.165 6.780 6.622 7.004 ns
GCLK t_co 3.364
4mA
GCLK
PLL ^tco
3.754
3.364
3.754
4.777 5.176 5.700 5.569 5.863 5.176 5.700 5.569 5.863 ns
5.353 5.809 6.388 6.230 6.612 5.809 6.388 6.230 6.612 ns
GCLK t_co 3.339
3.339 4.710 5.116 5.633 5.502 5.796 5.116 5.633 5.502 5.796 ns
6mA
GCLK
PLL ^tco
3.729
3.729 5.286 5.749 6.321 6.163 6.545 5.749 6.321 6.163 6.545 ns
1.5 V
GCLK t_co 3.328
3.328 4.693 5.091 5.613 5.482 5.776 5.091 5.613 5.482 5.776 ns
8mA
GCLK
PLL ^tco
3.718
3.718 5.269 5.724 6.301 6.143 6.525 5.724 6.301 6.143 6.525 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.273
3.663
3.273
3.663
4.655 5.041 5.543 5.412 5.706 5.041 5.543 5.412 5.706 ns
5.231 5.673 6.231 6.073 6.455 5.673 6.231 6.073 6.455 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.268
3.658
3.268
3.658
4.639 5.029 5.532 5.401 5.695 5.029 5.532 5.401 5.695 ns
5.214 5.662 6.220 6.062 6.444 5.662 6.220 6.062 6.444 ns
GCLK t_co 3.492
2mA
GCLK
PLL ^tco
3.882
3.492
3.882
5.022 5.468 6.036 5.905 6.199 5.468 6.036 5.905 6.199 ns
5.598 6.101 6.724 6.566 6.948 6.101 6.724 6.566 6.948 ns
GCLK t_co 3.369
3.369 4.797 5.207 5.750 5.619 5.913 5.207 5.750 5.619 5.913 ns
4mA
GCLK
PLL ^tco
3.759
3.759 5.372 5.839 6.438 6.280 6.662 5.839 6.438 6.280 6.662 ns
1.2 V
GCLK t_co 3.331
3.331 4.704 5.117 5.637 5.506 5.800 5.117 5.637 5.506 5.800 ns
6mA
GCLK
PLL ^tco
3.721
3.721 5.280 5.750 6.325 6.167 6.549 5.750 6.325 6.167 6.549 ns
GCLK t_co 3.284
8mA
GCLK
PLL ^tco
3.674
3.284
3.674
4.676 5.068 5.581 5.450 5.744 5.068 5.581 5.450 5.744 ns
5.252 5.701 6.269 6.111 6.493 5.701 6.269 6.111 6.493 ns
GCLK t_co 3.284
8mA
GCLK
PLL ^tco
3.674
3.284
3.674
4.633 5.016 5.512 5.381 5.675 5.016 5.512 5.381 5.675 ns
5.209 5.648 6.200 6.042 6.424 5.648 6.200 6.042 6.424 ns
SSTL-2
CLASS I
GCLK t_co
10mA _GCLK
PLL ^tco
3.281
3.671
3.281
3.671
4.630 5.012 5.508 5.377 5.671 5.012 5.508 5.377 5.671 ns
5.206 5.645 6.196 6.038 6.420 5.645 6.196 6.038 6.420 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.279
3.669
3.279
3.669
4.630 5.013 5.509 5.378 5.672 5.013 5.509 5.378 5.672 ns
5.206 5.646 6.197 6.039 6.421 5.646 6.197 6.039 6.421 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2