EP3SE80F780I4N Datasheet, PDF (73/341 Pages) Altera Corporation – Chapter Revision Dates

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–63
Table 1–48. EP3SL50 Row Pins Output Timing Parameters (Part 2 of 4)
I/O Standard
Clock
Fast Model
Industrial Commercial
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
RSDS_E_1R
GCLK t_co 3.082
—
GCLK
PLL ^tco
3.093
3.315
3.325
4.710 5.123 5.649 5.505 5.704 5.258 5.787 5.643 5.772 ns
4.711 5.124 5.648 5.504 5.703 5.257 5.785 5.641 5.770 ns
RSDS_E_3R
GCLK t_co 3.083
—
GCLK
PLL ^tco
3.069
3.316
3.302
4.709 5.122 5.647 5.503 5.702 5.257 5.785 5.641 5.770 ns
4.694 5.107 5.633 5.489 5.688 5.242 5.770 5.626 5.755 ns
DIFFERENTIAL
GCLK t_co
1.2-V
4mA _GCLK
HSTL CLASS I
PLL ^tco
3.066
3.063
3.298
3.296
4.690 5.103 5.629 5.485 5.684 5.238 5.766 5.622 5.751 ns
4.691 5.106 5.632 5.488 5.687 5.241 5.770 5.626 5.755 ns
DIFFERENTIAL
GCLK t_co
1.2-V
6mA _GCLK
HSTL CLASS I
PLL ^tco
3.064
3.113
3.296
3.349
4.681 5.094 5.619 5.475 5.674 5.228 5.756 5.612 5.741 ns
4.752 5.167 5.695 5.551 5.750 5.302 5.832 5.688 5.817 ns
DIFFERENTIAL
GCLK t_co
1.2-V
8mA _GCLK
HSTL CLASS I
PLL ^tco
3.089
3.071
3.325
3.306
4.734 5.150 5.678 5.534 5.733 5.285 5.817 5.673 5.802 ns
4.712 5.128 5.656 5.512 5.711 5.263 5.795 5.651 5.780 ns
DIFFERENTIAL
GCLK t_co
1.5-V
4mA _GCLK
HSTL CLASS I
PLL ^tco
3.117
3.102
3.352
3.337
4.752 5.167 5.694 5.550 5.749 5.302 5.832 5.688 5.817 ns
4.738 5.152 5.679 5.535 5.734 5.287 5.817 5.673 5.802 ns
DIFFERENTIAL
GCLK t_co
1.5-V
6mA _GCLK
HSTL CLASS I
PLL ^tco
3.091
3.071
3.326
3.306
4.733 5.149 5.676 5.532 5.731 5.284 5.815 5.671 5.800 ns
4.710 5.125 5.653 5.509 5.708 5.261 5.791 5.647 5.776 ns
DIFFERENTIAL
GCLK t_co
1.5-V
8mA _GCLK
HSTL CLASS I
PLL ^tco
3.068
3.073
3.302
3.306
4.706 5.122 5.649 5.505 5.704 5.257 5.788 5.644 5.773 ns
4.697 5.110 5.635 5.491 5.690 5.244 5.772 5.628 5.757 ns
DIFFERENTIAL
GCLK t_co
1.8-V
4mA _GCLK
HSTL CLASS I
PLL ^tco
3.066
3.094
3.299
3.328
4.696 5.111 5.638 5.494 5.693 5.247 5.777 5.633 5.762 ns
4.724 5.138 5.664 5.520 5.719 5.273 5.802 5.658 5.787 ns
DIFFERENTIAL
GCLK t_co
1.8-V
6mA _GCLK
HSTL CLASS I
PLL ^tco
3.076
3.062
3.311
3.295
4.709 5.123 5.649 5.505 5.704 5.258 5.787 5.643 5.772 ns
4.686 5.099 5.624 5.480 5.679 5.234 5.762 5.618 5.747 ns
DIFFERENTIAL
GCLK t_co
1.8-V
8mA _GCLK
HSTL CLASS I
PLL ^tco
2.668
3.062
2.842
3.288
3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.795 4.940 ns
4.646 5.055 5.575 5.431 5.630 5.186 5.709 5.565 5.694 ns
DIFFERENTIAL
GCLK t_co
1.8-V
10mA _GCLK
HSTL CLASS I
PLL ^tco
3.044
2.668
3.278
2.842
4.684 5.101 5.629 5.485 5.684 5.237 5.770 5.626 5.755 ns
3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.795 4.940 ns
DIFFERENTIAL
GCLK t_co
1.8-V
12mA _GCLK
HSTL CLASS I
PLL ^tco
3.062
3.044
3.288
3.278
4.646 5.055 5.575 5.431 5.630 5.186 5.709 5.565 5.694 ns
4.684 5.101 5.629 5.485 5.684 5.237 5.770 5.626 5.755 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2