EP3SE80F780I4N Datasheet, PDF (335/341 Pages) Altera Corporation – Chapter Revision Dates

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–325
Table 1–200 and Table 1–201 list the periphery clock timing parameters for EP3SE260
devices.
Table 1–200. EP3SE260 Column Pin Periphery Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
C2
C3
C4
C4L
Industrial
1.709
1.709
0.037
0.037
Commercial
1.716
1.716
0.037
0.037
V_CCL=
1.1 V
V_CCL=
1.1 V
2.620 2.765
2.620 2.765
-0.202 -0.213
-0.202 -0.213
V_CCL=
1.1 V
3.177
3.177
-0.140
-0.140
V_CCL=
1.1 V
3.039
3.039
-0.119
-0.119
V_CCL=
0.9 V
3.668
3.668
0.075
0.075
I3
V_CCL=
1.1 V
2.765
2.765
-0.213
-0.213
I4
V_CCL=
1.1 V
3.177
3.177
0.293
0.293
I4L
V_CCL=
1.1 V
3.039
3.039
-0.119
-0.119
V_CCL=
0.9 V
3.668
3.668
0.075
0.075
Units
ns
ns
ns
ns
Table 1–201. EP3SE260 Row Pin Periphery Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
Industrial Commercial
1.495
1.413
0.065
-0.017
1.574
1.483
0.172
0.081
C2
C3
C4
V_CCL=
1.1 V
V_CCL=
1.1 V
V_CCL=
1.1 V
2.378 2.518 2.878
2.223 2.355 2.697
-0.084 -0.118 -0.103
-0.236 -0.281 -0.284
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.776 3.072
2.605 2.913
-0.033 -0.071
-0.204 -0.230
I3
V_CCL=
1.1 V
2.555
2.385
-0.103
-0.273
I4
V_CCL=
1.1 V
2.926
2.737
0.384
0.195
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.776 3.072
2.605 2.913
-0.033 -0.071
-0.204 -0.230
Units
ns
ns
ns
ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2