EP3SE80F780I4N Datasheet, PDF (184/341 Pages) Altera Corporation – Chapter Revision Dates

1–174
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–89 and Table 1–90 list the EP3SL200 regional clock (RCLK) adder values that
must be added to the GCLK values. Use these adder values to determine I/O timing
when the I/O pin is driven using the regional clock. This applies to all I/O standards
supported by Stratix III devices.
Table 1–89 lists the EP3SL200 column pin delay adders when using the regional clock.
Table 1–89. EP3SL200 Column Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
Industrial Commercial
0.204
0.036
-0.211
1.904
0.235
0.046
-0.234
1.965
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
0.378 0.378 0.403 0.392 0.509 0.387 0.411 0.392 0.509 ns
0.078 0.078 -0.047 -0.038 -0.036 0.085 -0.046 -0.038 -0.036 ns
-0.332 -0.328 -0.34 -0.334 -0.464 -0.327 -0.339 -0.334 -0.464 ns
3.193 3.323 3.688 3.496 3.804 3.351 3.716 3.496 3.804 ns
Table 1–90 lists the EP3SL200 row pin delay adders when using the regional clock.
Table 1–90. EP3SL200 Row Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
Industrial Commercial
0.272
0.14
-0.278
-0.15
0.301
0.149
-0.306
-0.15
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
0.446 0.424 0.473 0.46 0.547 0.454 0.481 0.46 0.547 ns
0.226 0.216 0.235 0.226 0.306 0.232 0.254 0.226 0.306 ns
-0.418 -0.434 -0.486 -0.472 -0.592 -0.464 -0.493 -0.472 -0.592 ns
-0.227 -0.233 -0.254 -0.243 -0.322 -0.243 -0.258 -0.243 -0.322 ns
EP3SL340 I/O Timing Parameters
Table 1–91 through Table 1–94 list the maximum I/O timing parameters for EP3SL340
devices for single-ended I/O standards.
Table 1–91 lists the EP3SL340 column pins input timing parameters for single-ended
I/O standards.
Table 1–91. EP3SL340 Column Pins Input Timing Parameters (Part 1 of 4)
I/O
Standard
Clock
GCLK ^tsu
t_h
3.3-V LVTTL
GCLK ^tsu
PLL _th
3.3-V
LVCMOS
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
-1.345
-1.335 -2.017 -2.061 -2.330 -2.245 -2.542 -2.061 -2.330 -2.245 -2.542 ns
1.486
1.476 2.232 2.284 2.574 2.476 2.783 2.284 2.574 2.476 2.783 ns
-1.691
-1.691 -2.554 -2.585 -2.890 -2.799 -3.373 -2.585 -2.890 -2.799 -3.373 ns
1.996
1.996 3.031 3.081 3.434 3.313 3.912 3.081 3.434 3.313 3.912 ns
-1.345
-1.335 -2.017 -2.061 -2.330 -2.245 -2.542 -2.061 -2.330 -2.245 -2.542 ns
1.486
1.476 2.232 2.284 2.574 2.476 2.783 2.284 2.574 2.476 2.783 ns
-1.691
-1.691 -2.554 -2.585 -2.890 -2.799 -3.373 -2.585 -2.890 -2.799 -3.373 ns
1.996
1.996 3.031 3.081 3.434 3.313 3.912 3.081 3.434 3.313 3.912 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation